Re: [PATCH V4 00/11] perf/core: Add ability for an event to "pause" or "resume" AUX area tracing

From: Ian Rogers
Date: Wed Jan 31 2024 - 12:04:35 EST


On Mon, Jan 29, 2024 at 4:49 AM Adrian Hunter <adrian.hunter@xxxxxxxxx> wrote:
>
> On 11/01/24 10:19, Adrian Hunter wrote:
> > Hi
> >
> > Hardware traces, such as instruction traces, can produce a vast amount of
> > trace data, so being able to reduce tracing to more specific circumstances
> > can be useful.
> >
> > The ability to pause or resume tracing when another event happens, can do
> > that.
> >
> > These patches add such a facilty and show how it would work for Intel
> > Processor Trace.
> >
> > Maintainers of other AUX area tracing implementations are requested to
> > consider if this is something they might employ and then whether or not
> > the ABI would work for them.
> >
> > Changes to perf tools are now (since V4) fleshed out.
> >
> >
> > Changes in V4:
> >
> > perf/core: Add aux_pause, aux_resume, aux_start_paused
> > Rename aux_output_cfg -> aux_action
> > Reorder aux_action bits from:
> > aux_pause, aux_resume, aux_start_paused
> > to:
> > aux_start_paused, aux_pause, aux_resume
> > Fix aux_action bits __u64 -> __u32
> >
> > coresight: Have a stab at support for pause / resume
> > Dropped
> >
> > perf tools
> > All new patches
> >
> > Changes in RFC V3:
> >
> > coresight: Have a stab at support for pause / resume
> > 'mode' -> 'flags' so it at least compiles
> >
> > Changes in RFC V2:
> >
> > Use ->stop() / ->start() instead of ->pause_resume()
> > Move aux_start_paused bit into aux_output_cfg
> > Tighten up when Intel PT pause / resume is allowed
> > Add an example of how it might work for CoreSight
>
> Any more comments?

I think the tools side looks good. The parsing changes match the
existing style. I wonder if it wouldn't be better to handle the valid
strings (pause, resume, etc.) in the lexer rather than a separate
parse function, but the pattern used matches the existing one. You can
have my Acked-by on the tools changes, although the subtleties of ARM
PMUs makes me somewhat nervous in this regard.

Thanks,
Ian