Re: [PATCH 2/9] dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit

From: Peter Griffin
Date: Mon Jan 29 2024 - 04:19:30 EST

Hi André

On Sat, 27 Jan 2024 at 00:19, André Draszik <andre.draszik@xxxxxxxxxx> wrote:
>
> Add dt-schema documentation and clock IDs for the Connectivity
> Peripheral 1 (PERIC1) clock management unit.
>
> Signed-off-by: André Draszik <andre.draszik@xxxxxxxxxx>
>
> ---

Thanks for working on these regexes! That should make enabling more
clock units and other Exynos SoCs a bit easier.

Reviewed-by: Peter Griffin <peter.griffin@xxxxxxxxxx>

> Note for future reference: To ensure consistent naming throughout this
> file, the IDs have been derived from the data sheet using the
> following, with the expectation for all future additions to this file
> to use the same:
> sed \
> -e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|CLK_FOUT_\1_PLL|' \
> \
> -e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_|CLK_MOUT_\1_|' \
> -e 's|^PLL_CON0_PLL_\(.*\)|CLK_MOUT_PLL_\1|' \
> -e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|CLK_MOUT_\1|' \
> -e '/^PLL_CON[1-4]_[^_]\+_/d' \
> -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
> -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
> \
> -e 's|_IPCLKPORT||' \
> -e 's|_RSTNSYNC||' \
> \
> -e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_|CLK_DOUT_\1_|' \
> \
> -e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_|CLK_GOUT_\1_|' \
> -e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_|CLK_GOUT_\1_|' \
> -e 's|^CLK_GOUT_[^_]\+_[^_]\+_CMU_\([^_]\+\)_PCLK$|CLK_GOUT_\1_PCLK|' \
> -e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_|CLK_GOUT_\1_|' \
> -e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|CLK_GOUT_\1_CLK_\1_\2|' \
> \
> -e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d'
> ---
> .../bindings/clock/google,gs101-clock.yaml | 9 ++--
> include/dt-bindings/clock/google,gs101.h | 48 +++++++++++++++++++
> 2 files changed, 54 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> index 03698cdecf7a..1d2bcea41c85 100644
> --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -31,6 +31,7 @@ properties:
> - google,gs101-cmu-apm
> - google,gs101-cmu-misc
> - google,gs101-cmu-peric0
> + - google,gs101-cmu-peric1
>
> clocks:
> minItems: 1
> @@ -93,15 +94,17 @@ allOf:
> properties:
> compatible:
> contains:
> - const: google,gs101-cmu-peric0
> + enum:
> + - google,gs101-cmu-peric0
> + - google,gs101-cmu-peric1
>
> then:
> properties:
> clocks:
> items:
> - description: External reference clock (24.576 MHz)
> - - description: Connectivity Peripheral 0 bus clock (from CMU_TOP)
> - - description: Connectivity Peripheral 0 IP clock (from CMU_TOP)
> + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
> + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
>
> clock-names:
> items:
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> index 64e6bdc6359c..3dac3577788a 100644
> --- a/include/dt-bindings/clock/google,gs101.h
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -470,4 +470,52 @@
> #define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78
> #define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79
>
> +/* CMU_PERIC1 */
> +#define CLK_MOUT_PERIC1_BUS_USER 1
> +#define CLK_MOUT_PERIC1_I3C_USER 2
> +#define CLK_MOUT_PERIC1_USI0_USI_USER 3
> +#define CLK_MOUT_PERIC1_USI10_USI_USER 4
> +#define CLK_MOUT_PERIC1_USI11_USI_USER 5
> +#define CLK_MOUT_PERIC1_USI12_USI_USER 6
> +#define CLK_MOUT_PERIC1_USI13_USI_USER 7
> +#define CLK_MOUT_PERIC1_USI9_USI_USER 8
> +#define CLK_DOUT_PERIC1_I3C 9
> +#define CLK_DOUT_PERIC1_USI0_USI 10
> +#define CLK_DOUT_PERIC1_USI10_USI 11
> +#define CLK_DOUT_PERIC1_USI11_USI 12
> +#define CLK_DOUT_PERIC1_USI12_USI 13
> +#define CLK_DOUT_PERIC1_USI13_USI 14
> +#define CLK_DOUT_PERIC1_USI9_USI 15
> +#define CLK_GOUT_PERIC1_IP 16
> +#define CLK_GOUT_PERIC1_PCLK 17
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19
> +#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20
> +#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21
> +#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22
> +#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
> +#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
> +
> #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
> --
> 2.43.0.429.g432eaa2c6b-goog
>