Re: [PATCH v2] powerpc/6xx: set High BAT Enable flag on G2_LE cores

[Christophe Leroy]

Le 24/01/2024 à 11:38, Matthias Schiffer a écrit :
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> 
> MMU_FTR_USE_HIGH_BATS is set for G2_LE cores and derivatives like e300cX,
> but the high BATs need to be enabled in HID2 to work. Add register
> definitions and add the needed setup to __setup_cpu_603.
> 
> This fixes boot on CPUs like the MPC5200B with STRICT_KERNEL_RWX enabled
> on systems where the flag has not been set by the bootloader already.
> 
> Fixes: e4d6654ebe6e ("powerpc/mm/32s: rework mmu_mapin_ram()")
> Signed-off-by: Matthias Schiffer <matthias.schiffer@xxxxxxxxxxxxxxx>

Reviewed-by: Christophe Leroy <christophe.leroy@xxxxxxxxxx>

> ---
> 
> v2:
> - Use the G2_LE name for cores that have this HID2 register
> - Extend __setup_cpu_603 instead of introducing a new setup function
> 
> 
>   arch/powerpc/include/asm/reg.h      |  2 ++
>   arch/powerpc/kernel/cpu_setup_6xx.S | 20 +++++++++++++++++++-
>   2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
> index 4ae4ab9090a2..ade5f094dbd2 100644
> --- a/arch/powerpc/include/asm/reg.h
> +++ b/arch/powerpc/include/asm/reg.h
> @@ -617,6 +617,8 @@
>   #endif
>   #define SPRN_HID2      0x3F8           /* Hardware Implementation Register 2 */
>   #define SPRN_HID2_GEKKO        0x398           /* Gekko HID2 Register */
> +#define SPRN_HID2_G2_LE        0x3F3           /* G2_LE HID2 Register */
> +#define  HID2_G2_LE_HBE        (1<<18)         /* High BAT Enable (G2_LE) */
>   #define SPRN_IABR      0x3F2   /* Instruction Address Breakpoint Register */
>   #define SPRN_IABR2     0x3FA           /* 83xx */
>   #define SPRN_IBCR      0x135           /* 83xx Insn Breakpoint Control Reg */
> diff --git a/arch/powerpc/kernel/cpu_setup_6xx.S b/arch/powerpc/kernel/cpu_setup_6xx.S
> index f29ce3dd6140..bfd3f442e5eb 100644
> --- a/arch/powerpc/kernel/cpu_setup_6xx.S
> +++ b/arch/powerpc/kernel/cpu_setup_6xx.S
> @@ -26,6 +26,15 @@ BEGIN_FTR_SECTION
>          bl      __init_fpu_registers
>   END_FTR_SECTION_IFCLR(CPU_FTR_FPU_UNAVAILABLE)
>          bl      setup_common_caches
> +
> +       /*
> +        * This assumes that all cores using __setup_cpu_603 with
> +        * MMU_FTR_USE_HIGH_BATS are G2_LE compatible
> +        */
> +BEGIN_MMU_FTR_SECTION
> +       bl      setup_g2_le_hid2
> +END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
> +
>          mtlr    r5
>          blr
>   _GLOBAL(__setup_cpu_604)
> @@ -115,6 +124,16 @@ SYM_FUNC_START_LOCAL(setup_604_hid0)
>          blr
>   SYM_FUNC_END(setup_604_hid0)
> 
> +/* Enable high BATs for G2_LE and derivatives like e300cX */
> +SYM_FUNC_START_LOCAL(setup_g2_le_hid2)
> +       mfspr   r11,SPRN_HID2_G2_LE
> +       oris    r11,r11,HID2_G2_LE_HBE@h
> +       mtspr   SPRN_HID2_G2_LE,r11
> +       sync
> +       isync
> +       blr
> +SYM_FUNC_END(setup_g2_le_hid2)
> +
>   /* 7400 <= rev 2.7 and 7410 rev = 1.0 suffer from some
>    * erratas we work around here.
>    * Moto MPC710CE.pdf describes them, those are errata
> @@ -495,4 +514,3 @@ _GLOBAL(__restore_cpu_setup)
>          mtcr    r7
>          blr
>   _ASM_NOKPROBE_SYMBOL(__restore_cpu_setup)
> -
> --
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