Re: [PATCH 1/2] dt-bindings: usb: dwc3: Add system bus request info

[Frank Li]

On Tue, Jan 23, 2024 at 05:51:48PM +0000, Conor Dooley wrote:
> On Tue, Jan 23, 2024 at 12:49:27PM -0500, Frank Li wrote:
> > On Tue, Jan 23, 2024 at 05:27:13PM +0000, Conor Dooley wrote:
> > > On Tue, Jan 23, 2024 at 12:02:05PM -0500, Frank Li wrote:
> > > > Add device tree binding allow platform overwrite default value of *REQIN in
> > > > GSBUSCFG0.
> > > 
> > > Why might a platform actually want to do this? Why does this need to be
> > > set at the board level and being aware of which SoC is in use is not
> > > sufficient for the driver to set the correct values?
> > 
> > In snps,dwc3.yaml, there are already similary proptery, such as
> > snps,incr-burst-type-adjustment. Use this method can keep whole dwc3 usb
> > driver keep consistent. And not all platform try enable hardware
> > dma_cohenrence. It is configable for difference platform.
> 
> When you say "platform", what do you mean? I understand that term to
> mean a combination of board, soc and firmware.

In my company's environment, "platform" is "board". I will use "board" in
future. Is it big difference here?

Frank 

> 
> > > > Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> > > > ---
> > > >  .../devicetree/bindings/usb/snps,dwc3.yaml    | 36 +++++++++++++++++++
> > > >  1 file changed, 36 insertions(+)
> > > > 
> > > > diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> > > > index 8f5d250070c78..43e7fea3f6798 100644
> > > > --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> > > > +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml
> > > > @@ -439,6 +439,42 @@ properties:
> > > >      items:
> > > >        enum: [1, 4, 8, 16, 32, 64, 128, 256]
> > > >  
> > > > +  snps,des-wr-reqinfo:
> > > > +    description: Value for DESEWRREQIN of GSBUSCFG0 register.
> > > > +      ----------------------------------------------------------------
> > > > +       MBUS_TYPE| bit[3]       |bit[2]       |bit[1]     |bit[0]
> > > > +      ----------------------------------------------------------------
> > > > +       AHB      |Cacheable     |Bufferable   |Privilegge |Data
> > > > +       AXI3     |Write Allocate|Read Allocate|Cacheable  |Bufferable
> > > > +       AXI4     |Allocate Other|Allocate     |Modifiable |Bufferable
> > > > +       AXI4     |Other Allocate|Allocate     |Modifiable |Bufferable
> > > > +       Native   |Same as AXI   |Same as AXI  |Same as AXI|Same as AXI
> > > > +      ----------------------------------------------------------------
> > > > +      The AHB, AXI3, AXI4, and PCIe busses use different names for certain
> > > > +      signals, which have the same meaning:
> > > > +      Bufferable = Posted
> > > > +      Cacheable = Modifiable = Snoop (negation of No Snoop)
> > > > +    $ref: /schemas/types.yaml#/definitions/uint8
> > > > +    maxItem: 15
> > > > +
> > > > +  snps,des-rd-reqinfo:
> > > > +    description: Value for DESRDREQIN of GSBUSCFG0 register. ref
> > > > +      snps,des-wr-reqinfo
> > > > +    $ref: /schemas/types.yaml#/definitions/uint8
> > > > +    maxItem: 15
> > > > +
> > > > +  snps,dat-wr-reqinfo:
> > > > +    description: Value for DATWRREQIN of GSBUSCFG0 register. ref
> > > > +      snps,des-wr-reqinfo
> > > > +    $ref: /schemas/types.yaml#/definitions/uint8
> > > > +    maxItem: 15
> > > > +
> > > > +  snps,des-wr-reqinfo:
> > > > +    description: Value for DATWRREQIN of GSBUSCFG0 register. ref
> > > > +      snps,des-wr-reqinfo
> > > > +    $ref: /schemas/types.yaml#/definitions/uint8
> > > > +    maxItem: 15
> > > > +
> > > >    num-hc-interrupters:
> > > >      maximum: 8
> > > >      default: 1
> > > > -- 
> > > > 2.34.1
> > > > 
> > 
> >