Re: [PATCH 1/3] arm64: dts: qcom: sc8280xp: Fix PCIe PHY power-domains

[Johan Hovold]

On Mon, Jan 22, 2024 at 10:55:28PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Dec 29, 2023 at 10:33:34PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Dec 29, 2023 at 12:24:55PM +0100, Johan Hovold wrote:
> > > On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote:
> > > > The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other
> > > > hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators.
> > > 
> > > No, that does not seem to be entirely correct. I added the power-domains
> > > here precisely because they were needed to enable the PHYs.
> > > 
> > > This is something I stumbled over when trying to figure out how to
> > > add support for the second lane pair (i.e. four-lane mode), and I just
> > > went back and confirmed that this is still the case.
> > > 
> > > If you try to enable one of these PHYs without the corresponding GDSC
> > > being enabled, you end up with:
> > > 
> > > [   37.709324] ------------[ cut here ]------------
> > > [   37.718196] gcc_pcie_3b_aux_clk status stuck at 'off'
> > > [   37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c
> > > 	
> > 
> > Technically this patch is correct. PHYs are backed by MX domain only and not
> > GDSCs. Only the controllers (PCIe, UFS, USB) are backed by GDSCs. The fact that
> > you are seeing issue with PCIe Aux clock suggests me that this clock may not be
> > applicable to the PHY but it needs to be enabled for working of the PHY somehow.
> > I'll try to find the details on how exactly it is needed.
> > 
> > But if I get the answer like, "This clock is also sourced to PHY directly", then
> > we may need to add dual power domain for PHY (both GDSC and MX).
> > 
> 
> So I answer I got from Qcom is that this clock is only applicable to the PCIe
> controller and not PHYs. On some platforms, there is a separate PCIE_PHY_AUX_CLK
> coming from GCC that is used during L1SS state. I think that caused confusion
> while adding PHY support for followup platforms and folks just used PCIE_AUX_CLK
> since they couldn't find the actual PCIE_PHY_AUX_CLK.

Thanks for sorting that out.

> I've prepared a series to fix this mess, but I want to know how you end up
> seeing the above "clk status stuck at off" issue. Is there an actual usecase for
> powering up PHY without controller or you just experimented with it?

As I mentioned, I ran into this when experimenting with how to enable
the "companion" PHY for four-lane support. There shouldn't be any use
case for it (apart from using it to determine that the current
description of the PHY resources is incomplete or incorrect).

Johan