Re: [PATCH v11 03/10] spi: Add multi-cs memories support in SPI core

[Guenter Roeck]

On 1/20/24 17:04, Mark Brown wrote:
> On Sat, Jan 20, 2024 at 09:05:43AM -0800, Guenter Roeck wrote:
>
> > FWIW, the problem is due to
>
> > +#define SPI_CS_CNT_MAX 4
>
> > in the offending patch, but apeed2400 FMC supports up to 5 SPI chip selects.
> >
> >   static const struct aspeed_spi_data ast2400_fmc_data = {
> >          .max_cs        = 5,
> > 	^^^^^^^^^^^^^^^^^^^
> >          .hastype       = true,
>
> > Limiting .max_cs to 4 or increasing SPI_CS_CNT_MAX to 5 fixes the problem,
> > though of course I don't know if increasing SPI_CS_CNT_MAX has other side
> > effects.
>
> Yeah, I was coming to a similar conclusion myself - the limit is just
> too low.  I can't see any problem with increasing it.

It would cost a bit of memory and somewhat affect performance sine many
of the newly introduced loops are bound by SPI_CS_CNT_MAX and not by
num_chipselect.

It also might make sense to document the new limit somewhere. Prior
to this commit it was not limited at all.
Documentation/devicetree/bindings/spi/spi-davinci.txt lists 5 chip
selects in its example for the use of cs-gpios.
Documentation/devicetree/bindings/spi/spi-controller.yaml also does not
list a limit.

Thanks,
Guenter