RE: [PATCH v2] net: stmmac: Wait a bit for the reset to take effect

[Jose Abreu]

From: Bernd Edlinger <bernd.edlinger@xxxxxxxxxx>
Date: Wed, Jan 17, 2024 at 16:48:22

> I don't know at all.  And actually, I am more concerned that other registers
> might be unreliable within the first microsecond after reset is de-asserted.

Are you guaranteeing that the documented PoR time is achieved before reading registers?

> As I mentioned earlier the VHDL source code is obfuscated and I cannot
> tell anything about it, maybe people from synopsys can shed some light
> on the issue.

This ID must always be present; it should be different than zero.

Thanks,
Jose