Re: [PATCH 6/6] arm64: dts: qcom: ipq9574: Add RDP433 board device tree

[Lei Wei]

On 1/12/2024 11:05 PM, Dmitry Baryshkov wrote:
> On 10 January 2024 13:20:59 EET, Luo Jie <quic_luoj@xxxxxxxxxxx> wrote:
> > From: Lei Wei <quic_leiwei@xxxxxxxxxxx>
> >
> > RDP433 board has four QCA8075 PHYs and two Aquantia 10G PHY onboard.
> >
> > Signed-off-by: Lei Wei <quic_leiwei@xxxxxxxxxxx>
> > Signed-off-by: Luo Jie <quic_luoj@xxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 66 +++++++++++++++++++++
> > 1 file changed, 66 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> > index 1bb8d96c9a82..298c0853b4d2 100644
> > --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> > +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
> > @@ -60,3 +60,69 @@ rclk-pins {
> > 		};
> > 	};
> > };
> > +
> > +&qcom_ppe {
> > +	qcom,port_phyinfo {
> > +		ppe_port0: port@0 {
> > +			port_id = <1>;
> > +			phy-mode = "qsgmii";
> > +			phy-handle = <&phy0>;
> > +		};
> > +		ppe_port1: port@1 {
> > +			port_id = <2>;
> > +			phy-mode = "qsgmii";
> > +			phy-handle = <&phy1>;
> > +		};
> > +		ppe_port2: port@2 {
> > +			port_id = <3>;
> > +			phy-mode = "qsgmii";
> > +			phy-handle = <&phy2>;
> > +		};
> > +		ppe_port3: port@3 {
> > +			port_id = <4>;
> > +			phy-mode = "qsgmii";
> > +			phy-handle = <&phy3>;
> > +		};
> > +		ppe_port4: port@4 {
> > +			port_id = <5>;
> > +			phy-mode = "usxgmii";
> > +			phy-handle = <&phy4>;
> > +		};
> > +		ppe_port5: port@5 {
> > +			port_id = <6>;
> > +			phy-mode = "usxgmii";
> > +			phy-handle = <&phy5>;
> > +		};
> > +	};
> > +};
> > +
> > +&mdio {
> > +	reset-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>;
> > +	status = "okay";
> > +
> > +	phy0: ethernet-phy@0 {
> > +		      reg = <16>;
> > +	      };
>
> This part looks extremely wrong to me. If the reg is 16, then it should be @16 as well. You should have got a warning here.
Sure, I will fix and update it. Thanks.

> > +
> > +	phy1: ethernet-phy@1 {
> > +		      reg = <17>;
> > +	      };
> > +
> > +	phy2: ethernet-phy@2 {
> > +		      reg = <18>;
> > +	      };
> > +
> > +	phy3: ethernet-phy@3 {
> > +		      reg = <19>;
> > +	      };
> > +
> > +	phy4: ethernet-phy@4 {
> > +		      compatible ="ethernet-phy-ieee802.3-c45";
> > +		      reg = <8>;
> > +	      };
> > +
> > +	phy5: ethernet-phy@5 {
> > +		      compatible ="ethernet-phy-ieee802.3-c45";
> > +		      reg = <0>;
> > +	      };
> > +};