Re: [PATCH 2/6] dt-bindings: PCI: qcom,pcie-sm8450: move SM8450 to dedicated schema

[Rob Herring]

On Mon, Jan 08, 2024 at 03:19:15PM +0100, Krzysztof Kozlowski wrote:
> Move SM8450 PCIe devices from qcom,pcie.yaml binding to a dedicated file
> to make reviewing easier.
> 
> This creates equivalent schema file, except missing required compatible
> which is actually redundant.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
>  .../devicetree/bindings/pci/qcom,pcie-sm8450.yaml  | 215 +++++++++++++++++++++
>  .../devicetree/bindings/pci/qcom,pcie.yaml         |  67 -------
>  2 files changed, 215 insertions(+), 67 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
> new file mode 100644
> index 000000000000..59ba809b6204
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml
> @@ -0,0 +1,215 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8450.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM8450 PCI Express Root Complex
> +
> +maintainers:
> +  - Bjorn Andersson <andersson@xxxxxxxxxx>
> +  - Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> +
> +description:
> +  Qualcomm SM8450 SoC PCIe root complex controller is based on the Synopsys
> +  DesignWare PCIe IP.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - qcom,pcie-sm8450-pcie0
> +      - qcom,pcie-sm8450-pcie1
> +
> +  reg:
> +    minItems: 5
> +    maxItems: 6
> +
> +  reg-names:
> +    minItems: 5
> +    items:
> +      - const: parf # Qualcomm specific registers
> +      - const: dbi # DesignWare PCIe registers
> +      - const: elbi # External local bus interface registers
> +      - const: atu # ATU address space
> +      - const: config # PCIe configuration space
> +      - const: mhi # MHI registers
> +
> +  clocks:
> +    minItems: 11
> +    maxItems: 12
> +
> +  clock-names:
> +    minItems: 11
> +    maxItems: 12
> +
> +  resets:
> +    maxItems: 1
> +
> +  reset-names:
> +    items:
> +      - const: pci
> +
> +oneOf:
> +  - properties:
> +      interrupts:
> +        maxItems: 1
> +      interrupt-names:
> +        items:
> +          - const: msi
> +
> +  - properties:
> +      interrupts:
> +        minItems: 8
> +      interrupt-names:
> +        items:
> +          - const: msi0
> +          - const: msi1
> +          - const: msi2
> +          - const: msi3
> +          - const: msi4
> +          - const: msi5
> +          - const: msi6
> +          - const: msi7
> +
> +allOf:
> +  - $ref: qcom,pcie-common.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,pcie-sm8450-pcie0
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 12
> +          maxItems: 12
> +        clock-names:
> +          items:
> +            - const: pipe # PIPE clock
> +            - const: pipe_mux # PIPE MUX
> +            - const: phy_pipe # PIPE output clock
> +            - const: ref # REFERENCE clock
> +            - const: aux # Auxiliary clock
> +            - const: cfg # Configuration clock
> +            - const: bus_master # Master AXI clock
> +            - const: bus_slave # Slave AXI clock
> +            - const: slave_q2a # Slave Q2A clock
> +            - const: ddrss_sf_tbu # PCIe SF TBU clock
> +            - const: aggre0 # Aggre NoC PCIe0 AXI clock
> +            - const: aggre1 # Aggre NoC PCIe1 AXI clock
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,pcie-sm8450-pcie1
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 11
> +          maxItems: 11
> +        clock-names:
> +          items:
> +            - const: pipe # PIPE clock
> +            - const: pipe_mux # PIPE MUX
> +            - const: phy_pipe # PIPE output clock
> +            - const: ref # REFERENCE clock
> +            - const: aux # Auxiliary clock
> +            - const: cfg # Configuration clock
> +            - const: bus_master # Master AXI clock
> +            - const: bus_slave # Slave AXI clock
> +            - const: slave_q2a # Slave Q2A clock
> +            - const: ddrss_sf_tbu # PCIe SF TBU clock
> +            - const: aggre1 # Aggre NoC PCIe1 AXI clock

Almost the same list. Combine them and just make the 11th entry "enum: 
[aggre0, aggre1]".

Rob