Re: [PATCH 2/2] arm64: dts: imx93-phycore-segin: Add Phytec i.MX93 Segin

From: Fabio Estevam
Date: Tue Jan 16 2024 - 09:07:43 EST


On Tue, Jan 16, 2024 at 8:39 AM Mathieu Othacehe <othacehe@xxxxxxx> wrote:

> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 2e027675d7bb..6cb6d9f8783e 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -203,6 +203,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx93-phycore-segin.dtb

Please keep this in alphabetical order.

> +#include "imx93-phycore-som.dtsi"
> +
> +/{
> + model = "PHYTEC phyBOARD-Segin-i.MX93";
> + compatible = "phytec,imx93-phycore-segin",
> + "phytec,imx93-phycore-som", "fsl,imx93";

Can't the compatible be in a single line?

> + model = "PHYTEC phyCORE-i.MX93";
> + compatible = "phytec,imx93-phycore-som", "fsl,imx93";
> +
> + reserved-memory {
> + ranges;
> + #address-cells = <2>;
> + #size-cells = <2>;

Is this needed?

> +&iomuxc {
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
> + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
> + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
> + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
> + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
> + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
> + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
> + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
> + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
> + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
> + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
> + >;
> + };
> +

Please remove this blank line.
> +};