Re: [PATCH v7 2/4] dt-bindings: clock: sophgo: support SG2042

[Chen Wang]

Conor and Krzysztof,

Just a quick question, due to I am planning to change the binding files 
you have reviewed,  should I remain your signature of “Reviewed-by" or 
remove it in next patchset?

On 2024/1/12 15:42, Conor Dooley wrote:
> On Fri, Jan 12, 2024 at 08:08:15AM +0800, Chen Wang wrote:
> > On 2024/1/12 0:58, Conor Dooley wrote:
> > > On Thu, Jan 11, 2024 at 04:00:04PM +0800, Chen Wang wrote:
> > > > There are four types of clocks for SG2042 and following are where their
> > > > control registers are defined in:
> > > >
> > > > PLL：all in SYS_CTRL
> > > > DIV: all in CLOCK
> > > > GATE: some are in SYS_CTRL, some others are in CLOCK
> > > When you say "some", do you meant some entire clocks are in SYS_CTRL and
> > > some entire clocks are in the CLOCKS? Or do you meant that for a given
> > > clock, some registers are in SYS_CTRL and some are in CLOCK? It's the
> > > first option, right?
> > It's the first option.
> Then the gate clocks that are fully contained within SYS_CTRL are
> outputs of SYS_CTRL and gate clocks fully contained within CLOCK are
> outputs of CLOCK. You should not use a phandle to SYS_CTRL from the
> CLOCKS node so that you can pretend they are part of CLOCKS just because
> that makes writing your driver easier. That said, obviously you can
> share the routines for turning the gates on and off etc.
>
> Cheers,
> Conor.