RE: [EXT] Re: [RFC PATCH v2 0/2] Node migration between memory tiers

From: Srinivasulu Thanneeru
Date: Wed Jan 03 2024 - 02:56:57 EST

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Micron Confidential

Micron Confidential
+AD4- -----Original Message-----
+AD4- From: Huang, Ying +ADw-ying.huang+AEA-intel.com+AD4-
+AD4- Sent: Wednesday, January 3, 2024 11:38 AM
+AD4- To: Srinivasulu Thanneeru +ADw-sthanneeru+AEA-micron.com+AD4-
+AD4- Cc: gregory.price +ADw-gregory.price+AEA-memverge.com+AD4AOw- Srinivasulu Opensrc
+AD4- +ADw-sthanneeru.opensrc+AEA-micron.com+AD4AOw- linux-cxl+AEA-vger.kernel.org+ADs- linux-
+AD4- mm+AEA-kvack.org+ADs- aneesh.kumar+AEA-linux.ibm.com+ADs- dan.j.williams+AEA-intel.com+ADs-
+AD4- mhocko+AEA-suse.com+ADs- tj+AEA-kernel.org+ADs- john+AEA-jagalactic.com+ADs- Eishan Mirakhur
+AD4- +ADw-emirakhur+AEA-micron.com+AD4AOw- Vinicius Tavares Petrucci
+AD4- +ADw-vtavarespetr+AEA-micron.com+AD4AOw- Ravis OpenSrc +ADw-Ravis.OpenSrc+AEA-micron.com+AD4AOw-
+AD4- Jonathan.Cameron+AEA-huawei.com+ADs- linux-kernel+AEA-vger.kernel.org+ADs- Johannes
+AD4- Weiner +ADw-hannes+AEA-cmpxchg.org+AD4AOw- Wei Xu +ADw-weixugc+AEA-google.com+AD4-
+AD4- Subject: Re: +AFs-EXT+AF0- Re: +AFs-RFC PATCH v2 0/2+AF0- Node migration between memory
+AD4- tiers
+AD4-
+AD4- CAUTION: EXTERNAL EMAIL. Do not click links or open attachments unless
+AD4- you recognize the sender and were expecting this message.
+AD4-
+AD4-
+AD4- Srinivasulu Thanneeru +ADw-sthanneeru+AEA-micron.com+AD4- writes:
+AD4-
+AD4- +AD4- Micron Confidential
+AD4- +AD4-
+AD4- +AD4- Hi Huang, Ying,
+AD4- +AD4-
+AD4- +AD4- My apologies for wrong mail reply format, my mail client settings got
+AD4- changed on my PC.
+AD4- +AD4- Please find comments bellow inline.
+AD4- +AD4-
+AD4- +AD4- Regards,
+AD4- +AD4- Srini
+AD4- +AD4-
+AD4- +AD4-
+AD4- +AD4- Micron Confidential
+AD4- +AD4APg- -----Original Message-----
+AD4- +AD4APg- From: Huang, Ying +ADw-ying.huang+AEA-intel.com+AD4-
+AD4- +AD4APg- Sent: Monday, December 18, 2023 11:26 AM
+AD4- +AD4APg- To: gregory.price +ADw-gregory.price+AEA-memverge.com+AD4-
+AD4- +AD4APg- Cc: Srinivasulu Opensrc +ADw-sthanneeru.opensrc+AEA-micron.com+AD4AOw- linux-
+AD4- +AD4APg- cxl+AEA-vger.kernel.org+ADs- linux-mm+AEA-kvack.org+ADs- Srinivasulu Thanneeru
+AD4- +AD4APg- +ADw-sthanneeru+AEA-micron.com+AD4AOw- aneesh.kumar+AEA-linux.ibm.com+ADs-
+AD4- +AD4APg- dan.j.williams+AEA-intel.com+ADs- mhocko+AEA-suse.com+ADs- tj+AEA-kernel.org+ADs-
+AD4- +AD4APg- john+AEA-jagalactic.com+ADs- Eishan Mirakhur +ADw-emirakhur+AEA-micron.com+AD4AOw- Vinicius
+AD4- +AD4APg- Tavares Petrucci +ADw-vtavarespetr+AEA-micron.com+AD4AOw- Ravis OpenSrc
+AD4- +AD4APg- +ADw-Ravis.OpenSrc+AEA-micron.com+AD4AOw- Jonathan.Cameron+AEA-huawei.com+ADs- linux-
+AD4- +AD4APg- kernel+AEA-vger.kernel.org+ADs- Johannes Weiner +ADw-hannes+AEA-cmpxchg.org+AD4AOw- Wei Xu
+AD4- +AD4APg- +ADw-weixugc+AEA-google.com+AD4-
+AD4- +AD4APg- Subject: +AFs-EXT+AF0- Re: +AFs-RFC PATCH v2 0/2+AF0- Node migration between memory
+AD4- tiers
+AD4- +AD4APg-
+AD4- +AD4APg- CAUTION: EXTERNAL EMAIL. Do not click links or open attachments unless
+AD4- +AD4APg- you recognize the sender and were expecting this message.
+AD4- +AD4APg-
+AD4- +AD4APg-
+AD4- +AD4APg- Gregory Price +ADw-gregory.price+AEA-memverge.com+AD4- writes:
+AD4- +AD4APg-
+AD4- +AD4APg- +AD4- On Fri, Dec 15, 2023 at 01:02:59PM +-0800, Huang, Ying wrote:
+AD4- +AD4APg- +AD4APg- +ADw-sthanneeru.opensrc+AEA-micron.com+AD4- writes:
+AD4- +AD4APg- +AD4APg-
+AD4- +AD4APg- +AD4APg- +AD4- +AD0APQA9AD0APQA9AD0APQA9AD0APQA9AD0-
+AD4- +AD4APg- +AD4APg- +AD4- Version Notes:
+AD4- +AD4APg- +AD4APg- +AD4-
+AD4- +AD4APg- +AD4APg- +AD4- V2 : Changed interface to memtier+AF8-override from adistance+AF8-offset.
+AD4- +AD4APg- +AD4APg- +AD4- memtier+AF8-override was recommended by
+AD4- +AD4APg- +AD4APg- +AD4- 1. John Groves +ADw-john+AEA-jagalactic.com+AD4-
+AD4- +AD4APg- +AD4APg- +AD4- 2. Ravi Shankar +ADw-ravis.opensrc+AEA-micron.com+AD4-
+AD4- +AD4APg- +AD4APg- +AD4- 3. Brice Goglin +ADw-Brice.Goglin+AEA-inria.fr+AD4-
+AD4- +AD4APg- +AD4APg-
+AD4- +AD4APg- +AD4APg- It appears that you ignored my comments for V1 as follows ...
+AD4- +AD4APg- +AD4APg-
+AD4- +AD4APg- +AD4APg-
+AD4- +AD4APg-
+AD4- https://lore.k/
+AD4- +ACU-2F+ACY-data+AD0-05+ACU-7C02+ACU-7Csthanneeru+ACU-40micron.com+ACU-7C3e5d38eb47be463c2
+AD4- 95c08dc0c229d22+ACU-7Cf38a5ecd28134862b11bac1d563c806f+ACU-7C0+ACU-7C0+ACU-7C63
+AD4- 8398590664228240+ACU-7CUnknown+ACU-7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD
+AD4- AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0+ACU-3D+ACU-7C3000+ACU-7C+ACU-7C+ACU-7C
+AD4- +ACY-sdata+AD0-7fPxb1YYR2tZ0v2FB1vlXnMJFcI+ACU-2Fr9HT2+ACU-2BUD1MNUd+ACU-2FI+ACU-3D+ACY-re
+AD4- served+AD0-0
+AD4- +AD4APg- ernel.org+ACU-2Flkml+ACU-2F87o7f62vur.fsf+ACU-40yhuang6-
+AD4- +AD4APg-
+AD4- desk2.ccr.corp.intel.com+ACU-2F+ACY-data+AD0-05+ACU-7C02+ACU-7Csthanneeru+ACU-40micron.com
+AD4- +AD4APg-
+AD4- +ACU-7C5e614e5f028342b6b59c08dbff8e3e37+ACU-7Cf38a5ecd28134862b11bac1d56
+AD4- +AD4APg-
+AD4- 3c806f+ACU-7C0+ACU-7C0+ACU-7C638384758666895965+ACU-7CUnknown+ACU-7CTWFpbGZsb3d
+AD4- +AD4APg-
+AD4- 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0+ACU-3
+AD4- +AD4APg-
+AD4- D+ACU-7C3000+ACU-7C+ACU-7C+ACU-7C+ACY-sdata+AD0-OpMkYCar+ACU-2Fv8uHb7AvXbmaNltnXeTvcNUTi
+AD4- +AD4APg- bLhwV12Fg+ACU-3D+ACY-reserved+AD0-0
+AD4- +AD4-
+AD4- +AD4- Thank you, Huang, Ying for pointing to this.
+AD4- +AD4-
+AD4- https://lpc.ev/
+AD4- ents+ACU-2Fevent+ACU-2F16+ACU-2Fcontributions+ACU-2F1209+ACU-2Fattachments+ACU-2F1042+ACU-2F1
+AD4- 995+ACU-2FLive+ACU-2520In+ACU-2520a+ACU-2520World+ACU-2520With+ACU-2520Multiple+ACU-2520Me
+AD4- mory+ACU-2520Types.pdf+ACY-data+AD0-05+ACU-7C02+ACU-7Csthanneeru+ACU-40micron.com+ACU-7C3e
+AD4- 5d38eb47be463c295c08dc0c229d22+ACU-7Cf38a5ecd28134862b11bac1d563c806
+AD4- f+ACU-7C0+ACU-7C0+ACU-7C638398590664228240+ACU-7CUnknown+ACU-7CTWFpbGZsb3d8eyJW
+AD4- IjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0+ACU-3D+ACU-7C3
+AD4- 000+ACU-7C+ACU-7C+ACU-7C+ACY-sdata+AD0-1fGraxff7+ACU-2F1hNaE0an0xEudSKSUvaF3HgClMkmdC7
+AD4- n8+ACU-3D+ACY-reserved+AD0-0
+AD4- +AD4-
+AD4- +AD4- In the presentation above, the adistance+AF8-offsets are per memtype.
+AD4- +AD4- We believe that adistance+AF8-offset per node is more suitable and flexible.
+AD4- +AD4- since we can change it per node. If we keep adistance+AF8-offset per memtype,
+AD4- +AD4- then we cannot change it for a specific node of a given memtype.
+AD4- +AD4-
+AD4- +AD4APg- +AD4APg-
+AD4- +AD4APg-
+AD4- https://lore.k/
+AD4- +ACU-2F+ACY-data+AD0-05+ACU-7C02+ACU-7Csthanneeru+ACU-40micron.com+ACU-7C3e5d38eb47be463c2
+AD4- 95c08dc0c229d22+ACU-7Cf38a5ecd28134862b11bac1d563c806f+ACU-7C0+ACU-7C0+ACU-7C63
+AD4- 8398590664228240+ACU-7CUnknown+ACU-7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMD
+AD4- AiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0+ACU-3D+ACU-7C3000+ACU-7C+ACU-7C+ACU-7C
+AD4- +ACY-sdata+AD0-7fPxb1YYR2tZ0v2FB1vlXnMJFcI+ACU-2Fr9HT2+ACU-2BUD1MNUd+ACU-2FI+ACU-3D+ACY-re
+AD4- served+AD0-0
+AD4- +AD4APg- ernel.org+ACU-2Flkml+ACU-2F87jzpt2ft5.fsf+ACU-40yhuang6-
+AD4- +AD4APg-
+AD4- desk2.ccr.corp.intel.com+ACU-2F+ACY-data+AD0-05+ACU-7C02+ACU-7Csthanneeru+ACU-40micron.com
+AD4- +AD4APg-
+AD4- +ACU-7C5e614e5f028342b6b59c08dbff8e3e37+ACU-7Cf38a5ecd28134862b11bac1d56
+AD4- +AD4APg-
+AD4- 3c806f+ACU-7C0+ACU-7C0+ACU-7C638384758666895965+ACU-7CUnknown+ACU-7CTWFpbGZsb3d
+AD4- +AD4APg-
+AD4- 8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0+ACU-3
+AD4- +AD4APg-
+AD4- D+ACU-7C3000+ACU-7C+ACU-7C+ACU-7C+ACY-sdata+AD0-O0+ACU-2B6T+ACU-2FgU0TicCEYBac+ACU-2FAyjOLwAeouh
+AD4- +AD4APg- D+ACU-2BcMI+ACU-2BflOsI1M+ACU-3D+ACY-reserved+AD0-0
+AD4- +AD4-
+AD4- +AD4- Yes, memory+AF8-type would be grouping the related memories together as
+AD4- single tier.
+AD4- +AD4- We should also have a flexibility to move nodes between tiers, to address
+AD4- the issues.
+AD4- +AD4- described in use cases above.
+AD4-
+AD4- We don't pursue absolute flexibility. We add necessary flexibility
+AD4- only. Why do you need this kind of flexibility? Can you provide some
+AD4- use cases where memory+AF8-type based +ACI-adistance+AF8-offset+ACI- doesn't work?

- /sys/devices/virtual/memory+AF8-type/memory+AF8-type/ adistance+AF8-offset
memory+AF8-type based +ACI-adistance+AF8-offset will provide a way to move all nodes of same memory+AF8-type (e.g. all cxl nodes)
to different tier.

Whereas /sys/devices/system/node/node2/memtier+AF8-override provide a way migrate a node from one tier to another.
Considering a case where we would like to move two cxl nodes into two different tiers in future.
So, I thought it would be good to have flexibility at node level instead of at memory+AF8-type.

+AD4-
+AD4- --
+AD4- Best Regards,
+AD4- Huang, Ying

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