Re: [PATCH v2 1/3] perf/x86/amd/lbr: Use freeze based on availability

[Borislav Petkov]

On Tue, Jan 02, 2024 at 11:31:28AM +0530, Sandipan Das wrote:
> Currently, it is assumed that LBR Freeze is supported on all processors
> which have CPUID leaf 0x80000022[EAX] bit 1 set. This is incorrect as
> the feature availability is additionally dependent on CPUID leaf
> 0x80000022[EAX] bit 2 being set which may not be set for all Zen 4
> processors. Define a new feature bit for LBR and PMC freeze and set the
> freeze enable bit (FLBRI) in DebugCtl (MSR 0x1d9) conditionally.
> 
> It should still be possible to use LBR without freeze for profile-guided
> optimization of user programs by using an user-only branch filter during
> profiling. When the user-only filter is enabled, branches are no longer
> recorded after the transition to CPL 0 upon PMI arrival. When branch
> entries are read in the PMI handler, the branch stack does not change.
> 
> E.g.
> 
>   $ perf record -j any,u -e ex_ret_brn_tkn ./workload
> 
> Fixes: ca5b7c0d9621 ("perf/x86/amd/lbr: Add LbrExtV2 branch record support")
> Signed-off-by: Sandipan Das <sandipan.das@xxxxxxx>

Whoever ends up committing this, please add to the commit message the
reason why X86_FEATURE_AMD_LBR_PMC_FREEZE is left visible in
/proc/cpuinfo:

https://lore.kernel.org/all/CABPqkBQ0Zn_orR_9FnHA7Y1pNHAzG0E=86MkdMjOtGfKXDp29g@xxxxxxxxxxxxxx/

Thx.

-- 
Regards/Gruss,
    Boris.

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