Re: [PATCH v4 5/5] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform

[Krzysztof Kozlowski]

On 26/12/2023 08:25, Jie Luo wrote:
>>> -    description:
>>> -      the first Address and length of the register set for the MDIO controller.
>>> -      the second Address and length of the register for ethernet LDO, this second
>>> -      address range is only required by the platform IPQ50xx.
>>> +    maxItems: 5
>>> +    description: |
>>> +      The first address and length of the register set for the MDIO controller,
>>> +      the optional second address and length of the register is for CMN block,
>>> +      the optional third, fourth and fifth address and length of the register
>>> +      for Ethernet LDO, the optional Ethernet LDO address range is required by
>>
>> Wait, required? You said in in response to Rob these are not required!
> 
> As for the response to Rob, i was saying the uniphy ahb and sys clocks
> are not needed on ipq9574.
> The LDO are needed on ipq5332 and ipq5018 currently.

Clocks as well but:

"A driver can function without knowing about all these new registers and
..."

Anyway, this should be list ("items:") with descriptions, instead of one
big description listing things.


> 
>>
>>> +      the platform IPQ50xx/IPQ5332.
>>
>> So these are valid for all platforms or not? Looks not, but nothing
>> narrows the list for other boards.
> 
> i add the limitation on the reg usage for the ipq5332 platform on the
> following part "if condition" of this patch, i will update the patch
> to narrow down for the other compatibles.
> 
>>
>> Anyway, why do you add entries in the middle? LDO was the second, so it
>> cannot be now fifth.
> 
> As Rob's suggestion, i move the cmn_blk to second location for
> simplifying the limitation description, i checked the upstream dts code,
> the LDO is not used currently, so we can move cmn_blk to the second
> location here.

I cannot find his suggestion in the previous thread. Where did he
propose it?

...

>>> +  qcom,cmn-ref-clock-frequency:
>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>> +    enum:
>>> +      - 25000000
>>> +      - 31250000
>>> +      - 40000000
>>> +      - 48000000
>>> +      - 50000000
>>> +      - 96000000
>>> +    default: 48000000
>>> +    description: |
>>> +      The reference clock source of CMN PLL block is selectable, the
>>> +      reference clock source can be from wifi module or the external
>>> +      xtal, the reference clock frequency 48MHZ can be from internal
>>> +      wifi or the external xtal, if absent, the internal 48MHZ is used,
>>> +      if the 48MHZ is specified, which means the external 48Mhz is used.
>>
>> This does not resolve mine and Conor's concerns from previous version.
>> External clocks are defined as clock inputs.
> 
> No matter the external or internal reference clock, they are the clock
> source selection for CMN, there are only 48MHZ can be external or 
> internal, other clocks have the different clock rate, so the internal
> 48MHZ reference clock can be implied when the 
> "qcom,cmn-ref-clock-frequency" is not defined, which is suggested by 
> Conor in the previous
> comments.

I don't think he proposed it, but maybe I missed some message (care to
point me to his message where he agreed on usage of
qcom,cmn-ref-clock-frequency?). I am pretty sure we both stayed on the
same page, that the presence of clocks defines choice of internal clock.
This property should go away.

It is tiring to keep discussing this.

> 
>>
>>> +
>>> +  clock-frequency:
>>> +    enum:
>>> +      - 390625
>>> +      - 781250
>>> +      - 1562500
>>> +      - 3125000
>>> +      - 6250000
>>> +      - 12500000
>>> +    default: 390625
>>> +    description: |
>>> +      The MDIO bus clock that must be output by the MDIO bus hardware,
>>> +      only the listed frequencies above can be supported, other frequency
>>> +      will cause malfunction. If absent, the default hardware value 0xff
>>> +      is used, which means the default MDIO clock frequency 390625HZ, The
>>> +      MDIO clock frequency is MDIO_SYS_CLK/(MDIO_CLK_DIV + 1), the SoC
>>> +      MDIO_SYS_CLK is fixed to 100MHZ, the MDIO_CLK_DIV is from MDIO control
>>> +      register, there is higher clock frequency requirement on the normal
>>> +      working case where the MDIO slave devices support high clock frequency.
>>>   
>>>   required:
>>>     - compatible
>>> @@ -59,8 +118,10 @@ allOf:
>>>             contains:
>>>               enum:
>>>                 - qcom,ipq5018-mdio
>>> +              - qcom,ipq5332-mdio
>>>                 - qcom,ipq6018-mdio
>>>                 - qcom,ipq8074-mdio
>>> +              - qcom,ipq9574-mdio
>>>       then:
>>>         required:
>>>           - clocks
>>> @@ -70,6 +131,20 @@ allOf:
>>>           clocks: false
>>>           clock-names: false
>>>   
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - qcom,ipq5332-mdio
>>> +    then:
>>> +      properties:
>>> +        clocks:
>>> +          minItems: 5
>>> +          maxItems: 5
>>> +        reg-names:
>>> +          minItems: 4
>>
>> Why all other variants now have 5 clocks and 5 reg entries? Nothing of
>> it is explained in the commit msg.
> 
>  From the condition above, only "qcom,ipq5332-mdio" has 5 clocks (mdio +
> 4 uniphy clocks) and 4 regs (mdio + cmn_blk + 2 LDOs) as the cmn_blk is
> moved to the second location.
> 
> how it can gives the 5 clocks and 5 regs for other variants here?

How? Just read the beginning of your patch. It clearly says everyone has
up to 5 reg entries and up to 5 clocks.



Best regards,
Krzysztof