Re: [PATCH v8 14/14] dt-bindings: net: ar803x: add qca8084 PHY properties

From: Jie Luo
Date: Tue Dec 19 2023 - 03:53:41 EST



On 12/18/2023 5:34 PM, Andrew Lunn wrote:
Thanks Andrew for the proposal.
For the pure PHY chip qca8084, there is no driver to parse the package
level device tree node for common clocks and resets.

So you still have not look at the work Christian is doing. You must
work together with Christian. This driver is not going to be accepted
unless you do.
OK, Andrew, i am looking at Christian's patches on at803x.c, and i will
update qca8084 patches based on Christian's patch set.


ethernet-phy@0 {
compatible = "ethernet-phy-id004d.d180";
reg = <0>;
clocks = <qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>,
clock-names = <"gephy_sys">;
resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>,
<&qca8k_nsscc NSS_CC_GEPHY0_ARES>;
reset-names = "gephy_sys", "gephy_soft";

Which of these properties exist for the Pure PHY device? Which exist
for the integrated switch? And by that, i mean which are actual pins
on the PHY device? We need the device tree binding to list which
properties are required for each use case.

Andrew

Hi Andrew,
For the clocks and resets listed here, only the clock "mdio_master_ahb"
is dedicated in qca8386, others are needed on the both chips qca8386
and qca8084.

Here is the DTS example for the clocks and resets working on the
devices, from the example below, we can get the dedicated clocks
and resets for each MDIO device and package level device.

The DTS properties in the "qcom,phy-common" should be initialized by
the first PHY probe function, and only being initialized one time.

phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id004d.d180";
reg = <1>;

/* Package level configs, applicable on qca8386 and qca8081. */
phy-common-config {
qcom,phy-addr-fixup = <1 2 3 4 5 6 7>;
qcom,phy-work-mode = <2>;
clocks = <&qca8k_nsscc NSS_CC_APB_BRIDGE_CLK>,
<&qca8k_nsscc NSS_CC_AHB_CLK>,
<&qca8k_nsscc NSS_CC_SEC_CTRL_AHB_CLK>,
<&qca8k_nsscc NSS_CC_TLMM_CLK>,
<&qca8k_nsscc NSS_CC_TLMM_AHB_CLK>,
<&qca8k_nsscc NSS_CC_CNOC_AHB_CLK>,
<&qca8k_nsscc NSS_CC_MDIO_AHB_CLK>;


clock-names = "apb_bridge",
"ahb",
"sec_ctrl_ahb",
"tlmm",
"tlmm_ahb",
"cnoc_ahb",
"mdio_ahb";


resets = <&qca8k_nsscc NSS_CC_DSP_ARES>;
reset-names = "gephy_dsp";


ethernet-ports {
/* clocks and resets for pcs0. */
pcs0 {
clocks = <&qca8k_nsscc NSS_CC_SRDS0_SYS_CLK>;
clock-names = "srds0_sys";
resets = <&qca8k_nsscc NSS_CC_SRDS0_SYS_ARES>;
reset-names = "srds0_sys";
};

/* clocks and resets for pcs1. */
pcs1 {
clocks = <&qca8k_nsscc NSS_CC_SRDS1_SYS_CLK>;
clock-names = "srds1_sys";
resets = <&qca8k_nsscc NSS_CC_SRDS1_SYS_ARES>;
reset-names = "srds1_sys";
};

/* clocks and resets for first phy */
phy0 {
clocks = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_CLK>;
clock-names = "gephy0_sys";
resets = <&qca8k_nsscc NSS_CC_GEPHY0_SYS_ARES>,
<&qca8k_nsscc NSS_CC_GEPHY0_ARES>;
reset-names = "gephy0_sys",
"gephy0_soft";
};

/* clocks and resets for second phy */
phy1 {
clocks = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_CLK>;
clock-names = "gephy1_sys";
resets = <&qca8k_nsscc NSS_CC_GEPHY1_SYS_ARES>,
<&qca8k_nsscc NSS_CC_GEPHY1_ARES>;
reset-names = "gephy1_sys",
"gephy1_soft";
};

/* clocks and resets for third phy */
phy2 {
clocks = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_CLK>;
clock-names = "gephy2_sys";
resets = <&qca8k_nsscc NSS_CC_GEPHY2_SYS_ARES>,
<&qca8k_nsscc NSS_CC_GEPHY2_ARES>;
reset-names = "gephy2_sys",
"gephy2_soft";
};

/* clocks and resets for fourth phy */
phy3 {
clocks = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_CLK>;
clock-names = "gephy3_sys";
resets = <&qca8k_nsscc NSS_CC_GEPHY3_SYS_ARES>,
<&qca8k_nsscc NSS_CC_GEPHY3_ARES>;
reset-names = "gephy3_sys",
"gephy3_soft";
};


};
};

phy1: ethernet-phy@1 {
compatible = "ethernet-phy-id004d.d180";
reg = <2>;
};


phy2: ethernet-phy@2 {
compatible = "ethernet-phy-id004d.d180";
reg = <3>;
};


phy3: ethernet-phy@3 {
compatible = "ethernet-phy-id004d.d180";
reg = <4>;
};