[PATCH 09/10] arm64: dts: qcom: ipq5332: Add PCIe related nodes
From: Praveenkumar I
Date: Thu Dec 14 2023 - 01:31:02 EST
Add phy and controller nodes for pcie0_x1 and pcie1_x2.
Signed-off-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq5332.dtsi | 189 +++++++++++++++++++++++++-
1 file changed, 187 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index f0d92effb783..367641ab4938 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -166,6 +166,58 @@ usbphy0: phy@7b000 {
status = "disabled";
};
+ pcie0_phy: phy@4b0000{
+ compatible = "qcom,ipq5332-uniphy-pcie-gen3x1";
+ reg = <0x004b0000 0x800>;
+
+ clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>,
+ <&gcc GCC_SNOC_PCIE3_1LANE_M_CLK>,
+ <&gcc GCC_SNOC_PCIE3_1LANE_S_CLK>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK>;
+ clock-names = "pipe",
+ "lane_m",
+ "lane_s",
+ "phy_ahb";
+
+ resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>,
+ <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>,
+ <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>;
+ reset-names = "phy",
+ "phy_cfg",
+ "phy_ahb";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie0_pipe_clk_src";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@4b1000 {
+ compatible = "qcom,ipq5332-uniphy-pcie-gen3x2";
+ reg = <0x004b1000 0x1000>;
+
+ clocks = <&gcc GCC_PCIE3X2_PIPE_CLK>,
+ <&gcc GCC_SNOC_PCIE3_2LANE_M_CLK>,
+ <&gcc GCC_SNOC_PCIE3_2LANE_S_CLK>,
+ <&gcc GCC_PCIE3X2_PHY_AHB_CLK>;
+ clock-names = "pipe",
+ "lane_m",
+ "lane_s",
+ "phy_ahb";
+
+ resets = <&gcc GCC_PCIE3X2_PHY_BCR>,
+ <&gcc GCC_PCIE3X2_PHY_AHB_CLK_ARES>;
+ reset-names = "phy",
+ "phy_ahb";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie1_pipe_clk_src";
+
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
qfprom: efuse@a4000 {
compatible = "qcom,ipq5332-qfprom", "qcom,qfprom";
reg = <0x000a4000 0x721>;
@@ -211,9 +263,9 @@ gcc: clock-controller@1800000 {
#power-domain-cells = <1>;
clocks = <&xo_board>,
<&sleep_clk>,
+ <&pcie1_phy>,
<0>,
- <0>,
- <0>,
+ <&pcie0_phy>,
<0>;
};
@@ -359,6 +411,139 @@ usb_dwc: usb@8a00000 {
};
};
+ pcie0: pcie@20000000 {
+ compatible = "qcom,pcie-ipq5332";
+ reg = <0x20000000 0xf1d>,
+ <0x20000F20 0xa8>,
+ <0x20001000 0x1000>,
+ <0x00080000 0x3000>,
+ <0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0 0x20200000 0x20200000 0 0x00100000>, /* I/O */
+ <0x02000000 0 0x20300000 0x20300000 0 0x0fd00000>; /* MEM */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 35 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global_irq";
+
+ clocks = <&gcc GCC_PCIE3X1_0_AHB_CLK>,
+ <&gcc GCC_PCIE3X1_0_AUX_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X1_0_RCHG_CLK>;
+
+ clock-names = "ahb",
+ "aux",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE3X1_0_PIPE_ARES>,
+ <&gcc GCC_PCIE3X1_0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_M_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3X1_0_AXI_S_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X1_0_AUX_CLK_ARES>;
+
+ reset-names = "pipe",
+ "sticky",
+ "axi_m_sticky",
+ "axi_m",
+ "axi_s_sticky",
+ "axi_s",
+ "ahb",
+ "aux";
+
+ phys = <&pcie0_phy>;
+ phy-names = "pciephy";
+
+ msi-map = <0x0 &v2m0 0x0 0xffd>;
+ status = "disabled";
+ };
+
+ pcie1: pcie@18000000 {
+ compatible = "qcom,pcie-ipq5332";
+ reg = <0x18000000 0xf1d>,
+ <0x18000F20 0xa8>,
+ <0x18001000 0x1000>,
+ <0x00088000 0x3000>,
+ <0x18100000 0x1000>;
+ reg-names = "dbi", "elbi", "atu", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x01000000 0 0x18200000 0x18200000 0 0x00100000>, /* I/O */
+ <0x02000000 0 0x18300000 0x18300000 0 0x07d00000>; /* MEM */
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 412 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 413 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 414 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "global_irq";
+
+ clocks = <&gcc GCC_PCIE3X2_AHB_CLK>,
+ <&gcc GCC_PCIE3X2_AUX_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_M_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK>,
+ <&gcc GCC_PCIE3X2_AXI_S_BRIDGE_CLK>,
+ <&gcc GCC_PCIE3X2_RCHG_CLK>;
+
+ clock-names = "ahb",
+ "aux",
+ "axi_m",
+ "axi_s",
+ "axi_bridge",
+ "rchng";
+
+ resets = <&gcc GCC_PCIE3X2_PIPE_ARES>,
+ <&gcc GCC_PCIE3X2_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_M_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_M_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_S_STICKY_ARES>,
+ <&gcc GCC_PCIE3X2_AXI_S_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AHB_CLK_ARES>,
+ <&gcc GCC_PCIE3X2_AUX_CLK_ARES>;
+
+ reset-names = "pipe",
+ "sticky",
+ "axi_m_sticky",
+ "axi_m",
+ "axi_s_sticky",
+ "axi_s",
+ "ahb",
+ "aux";
+
+ phys = <&pcie1_phy>;
+ phy-names = "pciephy";
+ msi-map = <0x0 &v2m0 0x0 0xffd>;
+ status = "disabled";
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
--
2.34.1