[PATCH] [phy/renesas] phy-rcar-gen2: Add error handling

[Haoran Liu]

This patch introduces error handling for the clk_prepare_enable
call in the rcar_gen2_phy_init function within
drivers/phy/renesas/phy-rcar-gen2.c. Previously, the function
lacked appropriate handling for potential failures of
clk_prepare_enable, which could lead to instability if the clock
preparation failed.

Signed-off-by: Haoran Liu <liuhaoran14@xxxxxxx>
---
 drivers/phy/renesas/phy-rcar-gen2.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/renesas/phy-rcar-gen2.c b/drivers/phy/renesas/phy-rcar-gen2.c
index 507435af2656..c84eeaf1f607 100644
--- a/drivers/phy/renesas/phy-rcar-gen2.c
+++ b/drivers/phy/renesas/phy-rcar-gen2.c
@@ -80,6 +80,7 @@ static int rcar_gen2_phy_init(struct phy *p)
 	struct rcar_gen2_phy_driver *drv = channel->drv;
 	unsigned long flags;
 	u32 ugctrl2;
+	int ret;
 
 	/*
 	 * Try to acquire exclusive access to PHY.  The first driver calling
@@ -90,7 +91,11 @@ static int rcar_gen2_phy_init(struct phy *p)
 	if (cmpxchg(&channel->selected_phy, -1, phy->number) != -1)
 		return -EBUSY;
 
-	clk_prepare_enable(drv->clk);
+	ret = clk_prepare_enable(drv->clk);
+	if (ret) {
+		dev_err(&p->dev, "Failed to enable clock: %d\n", ret);
+		return ret;
+	}
 
 	spin_lock_irqsave(&drv->lock, flags);
 	ugctrl2 = readl(drv->base + USBHS_UGCTRL2);
-- 
2.17.1