Re: [PATCH net-next 2/2] net: phy: aquantia: enable USXGMII autoneg on AQR107

From: Robert Marko
Date: Tue Nov 28 2023 - 06:57:59 EST


On Fri, 17 Nov 2023 at 13:47, Russell King (Oracle)
<linux@xxxxxxxxxxxxxxx> wrote:
>
> On Fri, Nov 17, 2023 at 11:09:49AM +0100, Robert Marko wrote:
> > In case USXGMII is being used as the PHY interface mode then USXGMII
> > autoneg must be enabled as well.
> >
> > HW defaults to USXGMII autoneg being disabled which then results in
> > autoneg timeout, so enable it in case USXGMII is used.
>
> I was led to believe that the bitfield in bits 8:7 of the
> VEND1_GLOBAL_CFG_* registers, when set to value '1' is something
> to do with selecting USXGMII mode as opposed to 10GBASE-R. Could
> you look in to that and whether that is the more correct way of
> configuring the PHY for USXGMII mode?

Hi,

bits 8:7 in the VEND1_GLOBAL_CFG_* are used to configure the rate
adaptation method.
With the following allowed values:
0 (Default) = No rate adaptation
1 = USX rate adaptation
2 = Pause rate adaptation

I dont think that is related to the issue I am facing here which is
that by default
Bit 3 in the PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2 register
is set to 0.

This means that USX Autoneg Control For MAC is disabled and in USXGMII mode
auto-negotiation between the PHY and MAC will fail/timeout.

I have checked various vendor drivers and they all enable this bit in
case USXGMII
is used.

Regards,
Robert

>
> Thanks.
>
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