Re: [PATCH 07/16] arm64: dts: qcom: sm8550-aim300: add PCIe0

[Neil Armstrong]

Le 18/11/2023 à 01:08, Konrad Dybcio a écrit :
> On 17.11.2023 11:41, neil.armstrong@xxxxxxxxxx wrote:
> > On 17/11/2023 11:29, Dmitry Baryshkov wrote:
> > > On 17/11/2023 12:18, Tengfei Fan wrote:
> > > > Add PCIe0 nodes used with WCN7851 device.  The PCIe1 is not connected,
> > > > thus skip pcie_1_phy_aux_clk input clock to GCC.
> > > >
> > > > Signed-off-by: Tengfei Fan <quic_tengfan@xxxxxxxxxxx>
> > > > ---
> > > >    arch/arm64/boot/dts/qcom/sm8550-aim300.dts | 32 ++++++++++++++++++++++
> > > >    1 file changed, 32 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> > > > index 202b979da8ca..3aca0a433a00 100644
> > > > --- a/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> > > > +++ b/arch/arm64/boot/dts/qcom/sm8550-aim300.dts
> > > > @@ -393,6 +393,38 @@
> > > >        };
> > > >    };
> > > > +&gcc {
> > > > +    clocks = <&bi_tcxo_div2>, <&sleep_clk>,
> > > > +         <&pcie0_phy>,
> > > > +         <&pcie1_phy>,
> > > > +         <0>,
> > > > +         <&ufs_mem_phy 0>,
> > > > +         <&ufs_mem_phy 1>,
> > > > +         <&ufs_mem_phy 2>,
> > > > +         <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> > > > +};
> > >
> > > NAK, this should go to sm8550.dtsi unless there is a good reason.
> >
> > Actually this is how QRD8550 was designed, so it's fine to mimic.
> Does CCF not handle this gracefully?

CCF handles this very gracefully and it's a perfectly valid DT in regard
to the bindings...

neil

> Konrad