Re: [PATCH v5 3/6] net: phy: at803x: add QCA8084 ethernet phy support

[Russell King (Oracle)]

On Sat, Nov 18, 2023 at 04:51:42PM +0100, Andrew Lunn wrote:
> On Sat, Nov 18, 2023 at 02:27:51PM +0800, Luo Jie wrote:
> > Add qca8084 PHY support, which is four-port PHY with maximum
> > link capability 2.5G, the features of each port is almost same
> > as QCA8081 and slave seed config is not needed.
> > 
> > Three kind of interface modes supported by qca8084.
> > PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_2500BASEX and
> > PHY_INTERFACE_MODE_SGMII.
> 
> Sorry for joining the conversation late.
> 
> I'm trying to get my head around QXGMII. Let me describe what i think
> is happening, and then you can correct me....
> 
> You have 4 MACs, probably in a switch. The MII interfaces from these
> MACs go into a multiplexer, and out comes QXGMII? You then have a
> SERDES interface out of the switch and into the PHY package. Inside
> the PHY package there is a demultiplexor, giving you four MII
> interfaces, one to each PHY in the package.
> 
> If you have the PHY SERDES running in 2500BaseX, you have a single
> MAC, no mux/demux, and only one PHY is used? The other three are idle.
> Same from SGMII?
> 
> So the interface mode QXGMII is a property of the package. It is not
> really a property of one PHY. Having one PHY using QXGMII and another
> SGMII does not work?

10G_QXGMII is defined in the Cisco USXGMII multi-port document as one
of several possibilities for a USXGMII-M link. The Cisco document can
be a little confusing beause it states that 10G_QXGMII supports 10M,
100M, 1G and 2.5G, and then only talks about a 10G and 100M/1G MAC.

For 10G_QXGMII, there are 4 MAC interfaces. These are connected to a
rate "adaption" through symbol replication block, and then on to a
clause 49 PCS block.

There is then a port MUX and framing block, followed by the PMA
serdes which communicates with the remote end over a single pair of
transmit/receive serdes lines.

Each interface also has its own clause 37 autoneg block.

So, for an interface to operate in SGMII mode, it would have to be
muxed to a different path before being presented to the USXGMII-M
block since each interface does not have its own external data lane
- thus that's out of scope of USXGMII-M as documented by Cisco.

Hope this helps.

-- 
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