This commit describes the hardware layout for the sc8280xp for the[...]
following hardware blocks:
- 4 x VFE, 4 RDI per VFE
- 4 x VFE Lite, 4 RDI per VFE
- 4 x CSID
- 4 x CSID Lite
- 4 x CSI PHY
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@xxxxxxxxxx>
---
+static const struct camss_subdev_resources csid_res_sc8280xp[] = {(why is it 400, 400, 480, 600, 600, 600 and not 400, 480, 600?)
+ /* CSID0 */
+ {
+ .regulators = { "vdda-phy", "vdda-pll" },
+ .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_axi" },
+ .clock_rate = { { 400000000, 400000000, 480000000, 600000000, 600000000, 600000000 },
+ { 0 },There's a funny bug..
+ { 0 },
+ { 0 } },
+static const struct camss_subdev_resources vfe_res_sc8280xp[] = {Not the case here!
+ /* IFE0 */
+ {
+ .regulators = {},
+ .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb", "camnoc_axi", "vfe0", "vfe0_axi" },
+ .clock_rate = { { 0 },
+ { 0 },
+ { 19200000, 80000000, 80000000, 80000000, 80000000},
+ { 19200000, 150000000, 266666667, 320000000, 400000000, 480000000 },
+ { 400000000, 558000000, 637000000, 760000000 },
+ { 0 }, },