Re: [PATCH 2/2] phy: qcom-qmp-pcie: Add support for keeping refclk always on

[Krishna Chaitanya Chundru]

On 11/6/2023 9:47 PM, Bjorn Andersson wrote:
> On Mon, Nov 06, 2023 at 05:22:35PM +0530, Krishna chaitanya chundru wrote:
> > In PCIe low power states like L1.1 or L1.2 the phy will stop
> > supplying refclk to endpoint. If endpoint asserts clkreq to bring
> > back link L0, then RC needs to provide refclk to endpoint.
> >
> > If there is some issues in platform with clkreq signal propagation
> > to host and due to that host will not send refclk which results PCIe link
> > down. For those platforms  phy needs to provide refclk even in low power
> Double <space> ------------^^
ACK
> > states.
> >
> > Add a flag which indicates refclk is always supplied to endpoint.
> The patch itself look good, the problem description looks good, but if
> you have an indication that the refclk "is always supplied to the
> endpoint", then you don't have a problem with refclk and I don't think
> you need this patch.
>
> Something to the tune of "keep refclk always supplied to endpoint" seems
> to more appropriately describe what this flag is doing.
Sure I will change it in my next patch.
> > Signed-off-by: Krishna chaitanya chundru <quic_krichai@xxxxxxxxxxx>
> > ---
> >   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 21 +++++++++++++++++----
> >   1 file changed, 17 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > index a63ca7424974..d7e377a7d96e 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > @@ -43,6 +43,8 @@
> >   /* QPHY_PCS_STATUS bit */
> >   #define PHYSTATUS				BIT(6)
> >   #define PHYSTATUS_4_20				BIT(7)
> > +/* PCS_PCIE_ENDPOINT_REFCLK_CNTRL */
> > +#define EPCLK_ALWAYS_ON_EN			BIT(6)
> >   
> >   #define PHY_INIT_COMPLETE_TIMEOUT		10000
> >   
> > @@ -77,6 +79,7 @@ enum qphy_reg_layout {
> >   	QPHY_START_CTRL,
> >   	QPHY_PCS_STATUS,
> >   	QPHY_PCS_POWER_DOWN_CONTROL,
> > +	QPHY_PCS_ENDPOINT_REFCLK_CNTRL,
> >   	/* Keep last to ensure regs_layout arrays are properly initialized */
> >   	QPHY_LAYOUT_SIZE
> >   };
> > @@ -103,10 +106,11 @@ static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
> >   };
> >   
> >   static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
> > -	[QPHY_SW_RESET]			= QPHY_V4_PCS_SW_RESET,
> > -	[QPHY_START_CTRL]		= QPHY_V4_PCS_START_CONTROL,
> > -	[QPHY_PCS_STATUS]		= QPHY_V4_PCS_PCS_STATUS1,
> > -	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V4_PCS_POWER_DOWN_CONTROL,
> > +	[QPHY_SW_RESET]				= QPHY_V4_PCS_SW_RESET,
> > +	[QPHY_START_CTRL]			= QPHY_V4_PCS_START_CONTROL,
> > +	[QPHY_PCS_STATUS]			= QPHY_V4_PCS_PCS_STATUS1,
> > +	[QPHY_PCS_POWER_DOWN_CONTROL]		= QPHY_V4_PCS_POWER_DOWN_CONTROL,
> > +	[QPHY_PCS_ENDPOINT_REFCLK_CNTRL]	= QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL,
> >   };
> >   
> >   static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
> > @@ -2244,6 +2248,8 @@ struct qmp_pcie {
> >   	struct phy *phy;
> >   	int mode;
> >   
> > +	bool refclk_always_on;
> > +
> >   	struct clk_fixed_rate pipe_clk_fixed;
> >   };
> >   
> > @@ -3159,6 +3165,10 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c
> >   	qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num);
> >   	qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
> >   
> > +	if (qmp->refclk_always_on && cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL])
> > +		qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL],
> > +			     EPCLK_ALWAYS_ON_EN);
> > +
> >   	if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
> >   		qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
> >   		qmp_pcie_init_port_b(qmp, tbls);
> > @@ -3681,6 +3691,9 @@ static int qmp_pcie_probe(struct platform_device *pdev)
> >   	if (ret)
> >   		goto err_node_put;
> >   
> > +	qmp->refclk_always_on = of_property_read_bool(dev->of_node,
> > +						      "qcom,refclk-always-on");
> Leave this line unwrapped, for readability.
>
> Regards,
> Bjorn

sure I will update this in next patch.

- Krishna Chaitanya.

> > +
> >   	ret = phy_pipe_clk_register(qmp, np);
> >   	if (ret)
> >   		goto err_node_put;
> >
> > --
> > 2.42.0