[GIT PULL] Compute Express Link (CXL) for 6.7
From: Dan Williams
Date: Sat Nov 04 2023 - 16:51:36 EST
Hi Linus, please pull from:
git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-for-6.7
...to receive the CXL update for this cycle.
The main new functionality this time is work to allow Linux to natively
handle CXL link protocol errors signalled via PCIe AER for current
generation CXL platforms. This required some enlightenment of the PCIe
AER core to workaround the fact that current generation RCH (Restricted
CXL Host) platforms physically hide topology details and registers via a
mechanism called RCRB (Root Complex Register Block). It has a minor
conflict with the PCI updates you have already pulled this cycle, sample
resolution below.
The next major highlight is reworks to address bugs in parsing region
configurations for next generation VH (Virtual Host) topologies. The
old broken algorithm is replaced with a simpler one that significantly
increases the number of region configurations supported by Linux. This
is again relevant for error handling so that forward and reverse address
translation of memory errors can be carried out by Linux for memory
regions instantiated by platform firmware.
As for other cross-tree work, the ACPI table parsing code has been
refactored for reuse parsing the "CDAT" structure which is an ACPI-like
data structure that is reported by CXL devices. That work is in
preparation for v6.8 support for CXL QoS. Think of this as dynamic
generation of NUMA node topology information generated by Linux rather
than platform firmware.
Lastly, a number of internal object lifetime issues have been resolved
along with misc. fixes and feature updates (decoders_committed sysfs
ABI).
This has all appeared in -next with a few late breaking fixes applied
for reported issues, but otherwise no new reports since this past
Monday. The touches of PCI and ACPI have received acks from Bjorn and
Rafael respectively.
---
Proposed merge resolution:
diff --cc drivers/pci/pcie/aer.c
index dcd35993004e,41076cb2956e..42a3bd35a3e1
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@@ -997,16 -1142,7 +1143,16 @@@ static void aer_recover_work_func(struc
PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
continue;
}
- cper_print_aer(pdev, entry.severity, entry.regs);
+ pci_print_aer(pdev, entry.severity, entry.regs);
+ /*
+ * Memory for aer_capability_regs(entry.regs) is being allocated from the
+ * ghes_estatus_pool to protect it from overwriting when multiple sections
+ * are present in the error status. Thus free the same after processing
+ * the data.
+ */
+ ghes_estatus_pool_region_free((unsigned long)entry.regs,
+ sizeof(struct aer_capability_regs));
+
if (entry.severity == AER_NONFATAL)
pcie_do_recovery(pdev, pci_channel_io_normal,
aer_root_reset);
---
The following changes since commit 178e1ea6a68f12967ee0e9afc4d79a2939acd43c:
ACPICA: Add defines for CDAT SSLBIS (2023-10-03 16:04:22 +0200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl tags/cxl-for-6.7
for you to fetch changes up to 4b92894064b3df472b2cf5741c7f080e16dcd1ec:
lib/fw_table: Remove acpi_parse_entries_array() export (2023-11-02 15:17:21 -0700)
----------------------------------------------------------------
cxl for v6.7
- Add support for RCH (Restricted CXL Host) Error recovery
- Fix several region assembly bugs
- Fix mem-device lifetime issues relative to the sanitize command and
RCH topology.
- Refactor ACPI table parsing for CDAT parsing re-use in preparation for
CXL QOS support.
----------------------------------------------------------------
Alison Schofield (4):
cxl/mbox: Remove useless cast in cxl_mem_create_range_info()
cxl/region: Prepare the decoder match range helper for reuse
cxl/region: Calculate a target position in a region interleave
cxl/region: Use cxl_calc_interleave_pos() for auto-discovery
Dan Carpenter (1):
cxl/hdm: Fix && vs || bug
Dan Williams (19):
cxl/port: Quiet warning messages from the cxl_test environment
cxl/pci: Remove unnecessary device reference management in sanitize work
cxl/pci: Cleanup 'sanitize' to always poll
cxl/pci: Remove hardirq handler for cxl_request_irq()
cxl/pci: Remove inconsistent usage of dev_err_probe()
cxl/pci: Clarify devm host for memdev relative setup
cxl/pci: Fix sanitize notifier setup
cxl/memdev: Fix sanitize vs decoder setup locking
cxl/mem: Fix shutdown order
tools/testing/cxl: Make cxl_memdev_state available to other command emulation
tools/testing/cxl: Add 'sanitize notifier' support
cxl/port: Fix delete_endpoint() vs parent unregistration race
cxl/port: Fix @host confusion in cxl_dport_setup_regs()
Merge branch 'for-6.7/cxl-rch-eh' into cxl/next
Merge branch 'for-6.7/cxl-qtg' into cxl/next
Merge branch 'for-6.7/cxl' into cxl/next
Merge branch 'for-6.7/cxl-commited' into cxl/next
cxl/hdm: Remove broken error path
lib/fw_table: Remove acpi_parse_entries_array() export
Dave Jiang (6):
cxl: Add cxl_decoders_committed() helper
cxl: Add decoders_committed sysfs attribute to cxl_port
cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute
cxl: Add checksum verification to CDAT from CXL
cxl: Add support for reading CXL switch CDAT table
acpi: Move common tables helper functions to common lib
Ira Weiny (1):
cxl/pci: Update comment
Jim Harris (2):
cxl/region: Do not try to cleanup after cxl_region_setup_targets() fails
cxl/region: Fix x1 root-decoder granularity calculations
Li Zhijian (1):
cxl/region: Fix cxl_region_rwsem lock held when returning to user space
Robert Richter (12):
cxl/core/regs: Rename @dev to @host in struct cxl_register_map
cxl/port: Rename @comp_map to @reg_map in struct cxl_register_map
cxl/port: Pre-initialize component register mappings
cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state
cxl/hdm: Use stored Component Register mappings to map HDM decoder capability
cxl/pci: Remove Component Register base address from struct cxl_dev_state
cxl/port: Remove Component Register base address from struct cxl_port
cxl/pci: Add RCH downstream port AER register discovery
PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem dev handler
PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling
cxl/core/regs: Rename phys_addr in cxl_map_component_regs()
cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devm
Terry Bowman (6):
PCI/AER: Refactor cper_print_aer() for use by CXL driver module
cxl/pci: Update CXL error logging to use RAS register address
cxl/pci: Map RCH downstream AER registers for logging protocol errors
cxl/pci: Add RCH downstream port error logging
cxl/pci: Disable root port interrupts in RCH mode
cxl/pci: Change CXL AER support check to use native AER
Vishal Verma (2):
MAINTAINERS: Add tools/testing/cxl files to CXL
tools/testing/cxl: Slow down the mock firmware transfer
Documentation/ABI/testing/sysfs-bus-cxl | 30 ++++
MAINTAINERS | 3 +
drivers/acpi/Kconfig | 1 +
drivers/acpi/tables.c | 173 --------------------
drivers/cxl/acpi.c | 3 +
drivers/cxl/core/core.h | 2 +
drivers/cxl/core/hdm.c | 93 +++++------
drivers/cxl/core/mbox.c | 60 +++++--
drivers/cxl/core/memdev.c | 161 +++++++++----------
drivers/cxl/core/pci.c | 275 +++++++++++++++++++++++++++++---
drivers/cxl/core/port.c | 184 +++++++++++++++------
drivers/cxl/core/region.c | 266 +++++++++++++++++-------------
drivers/cxl/core/regs.c | 73 ++++++---
drivers/cxl/cxl.h | 38 +++--
drivers/cxl/cxlmem.h | 17 +-
drivers/cxl/mem.c | 7 +-
drivers/cxl/pci.c | 107 ++++++-------
drivers/cxl/port.c | 3 +
drivers/pci/pcie/Kconfig | 9 ++
drivers/pci/pcie/aer.c | 159 +++++++++++++++++-
include/linux/acpi.h | 42 ++---
include/linux/aer.h | 2 +-
include/linux/fw_table.h | 43 +++++
lib/Kconfig | 3 +
lib/Makefile | 2 +
lib/fw_table.c | 188 ++++++++++++++++++++++
tools/testing/cxl/test/cxl.c | 2 +-
tools/testing/cxl/test/mem.c | 83 ++++++++--
28 files changed, 1375 insertions(+), 654 deletions(-)
create mode 100644 include/linux/fw_table.h
create mode 100644 lib/fw_table.c