Re: [PATCH v1 1/3] PCI: qcom: Enable cache coherency for SA8775P RC

[Konrad Dybcio]

On 02/11/2023 11:16, Mrinmay Sarkar wrote:
> On 10/31/2023 10:20 PM, Konrad Dybcio wrote:
> > On 31.10.2023 16:46, Mrinmay Sarkar wrote:
> > > This change will enable cache snooping logic to support
> > > cache coherency for SA8755P RC platform.
> > 8775
> >
> > > Signed-off-by: Mrinmay Sarkar <quic_msarkar@xxxxxxxxxxx>
> > > ---
> > >   drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++
> > >   1 file changed, 11 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c 
> > > b/drivers/pci/controller/dwc/pcie-qcom.c
> > > index 6902e97..6f240fc 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > @@ -51,6 +51,7 @@
> > >   #define PARF_SID_OFFSET                0x234
> > >   #define PARF_BDF_TRANSLATE_CFG            0x24c
> > >   #define PARF_SLV_ADDR_SPACE_SIZE        0x358
> > > +#define PCIE_PARF_NO_SNOOP_OVERIDE        0x3d4
> > >   #define PARF_DEVICE_TYPE            0x1000
> > >   #define PARF_BDF_TO_SID_TABLE_N            0x2000
> > > @@ -117,6 +118,9 @@
> > >   /* PARF_LTSSM register fields */
> > >   #define LTSSM_EN                BIT(8)
> > > +/* PARF_NO_SNOOP_OVERIDE register value */
> > override
> > > +#define NO_SNOOP_OVERIDE_EN            0xa
> > is this actually some magic value and not BIT(1) | BIT(3)?
> we need to set 1st and 3rd bit. yes, we can use BIT(1) | BIT(3).
It would be great if you could explain what each of these bits means
separately, #defining them instead and ORing at usage time.

Konrad