Re: [PATCH v3 3/4] PCI: layerscape: Rename pf_* as pf_lut_*

[Frank Li]

On Thu, Nov 02, 2023 at 11:03:14PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 17, 2023 at 03:31:44PM -0400, Frank Li wrote:
> > 'pf' and 'lut' is just difference name in difference chips, but basic it is
> > a MMIO base address plus an offset.
> > 
> > Rename it to avoid duplicate pf_* and lut_* in driver.
> > 
> 
> "pci-layerscape-ep.c" uses "ls_lut_" prefix and now you are using "pf_lut_". May
> I know the difference between these two? Can we just use a common name?

Some chip use name lut, some chip use name pf. I think ls_pcie_pf_lut_*()
is better name then 'ls_lut_' in pci-layerscape-ep.c to align with spec. 

If need, I can rename "ls_lut_" in "pci-layerscape-ep.c" later.

Frank

> 
> - Mani
> 
> > Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> > ---
> > 
> > Notes:
> >     change from v1 to v3
> >     - new patch at v3
> > 
> >  drivers/pci/controller/dwc/pci-layerscape.c | 34 ++++++++++-----------
> >  1 file changed, 17 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
> > index 6f47cfe146c44..4b663b20d8612 100644
> > --- a/drivers/pci/controller/dwc/pci-layerscape.c
> > +++ b/drivers/pci/controller/dwc/pci-layerscape.c
> > @@ -46,7 +46,7 @@
> >  #define LS_PCIE_DRV_SCFG	BIT(0)
> >  
> >  struct ls_pcie_drvdata {
> > -	const u32 pf_off;
> > +	const u32 pf_lut_off;
> >  	const struct dw_pcie_host_ops *ops;
> >  	int (*exit_from_l2)(struct dw_pcie_rp *pp);
> >  	int flags;
> > @@ -56,13 +56,13 @@ struct ls_pcie_drvdata {
> >  struct ls_pcie {
> >  	struct dw_pcie *pci;
> >  	const struct ls_pcie_drvdata *drvdata;
> > -	void __iomem *pf_base;
> > +	void __iomem *pf_lut_base;
> >  	struct regmap *scfg;
> >  	int index;
> >  	bool big_endian;
> >  };
> >  
> > -#define ls_pcie_pf_readl_addr(addr)	ls_pcie_pf_readl(pcie, addr)
> > +#define ls_pcie_pf_lut_readl_addr(addr)	ls_pcie_pf_lut_readl(pcie, addr)
> >  #define to_ls_pcie(x)	dev_get_drvdata((x)->dev)
> >  
> >  static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
> > @@ -103,20 +103,20 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
> >  	iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
> >  }
> >  
> > -static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off)
> > +static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off)
> >  {
> >  	if (pcie->big_endian)
> > -		return ioread32be(pcie->pf_base + off);
> > +		return ioread32be(pcie->pf_lut_base + off);
> >  
> > -	return ioread32(pcie->pf_base + off);
> > +	return ioread32(pcie->pf_lut_base + off);
> >  }
> >  
> > -static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val)
> > +static void ls_pcie_pf_lut_writel(struct ls_pcie *pcie, u32 off, u32 val)
> >  {
> >  	if (pcie->big_endian)
> > -		iowrite32be(val, pcie->pf_base + off);
> > +		iowrite32be(val, pcie->pf_lut_base + off);
> >  	else
> > -		iowrite32(val, pcie->pf_base + off);
> > +		iowrite32(val, pcie->pf_lut_base + off);
> >  }
> >  
> >  static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
> > @@ -126,11 +126,11 @@ static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
> >  	u32 val;
> >  	int ret;
> >  
> > -	val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);
> > +	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);
> >  	val |= PF_MCR_PTOMR;
> > -	ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);
> > +	ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);
> >  
> > -	ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,
> > +	ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR,
> >  				 val, !(val & PF_MCR_PTOMR),
> >  				 PCIE_PME_TO_L2_TIMEOUT_US/10,
> >  				 PCIE_PME_TO_L2_TIMEOUT_US);
> > @@ -149,15 +149,15 @@ static int ls_pcie_exit_from_l2(struct dw_pcie_rp *pp)
> >  	 * Set PF_MCR_EXL2S bit in LS_PCIE_PF_MCR register for the link
> >  	 * to exit L2 state.
> >  	 */
> > -	val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR);
> > +	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_PF_MCR);
> >  	val |= PF_MCR_EXL2S;
> > -	ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val);
> > +	ls_pcie_pf_lut_writel(pcie, LS_PCIE_PF_MCR, val);
> >  
> >  	/*
> >  	 * L2 exit timeout of 10ms is not defined in the specifications,
> >  	 * it was chosen based on empirical observations.
> >  	 */
> > -	ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR,
> > +	ret = readx_poll_timeout(ls_pcie_pf_lut_readl_addr, LS_PCIE_PF_MCR,
> >  				 val, !(val & PF_MCR_EXL2S),
> >  				 1000,
> >  				 10000);
> > @@ -245,7 +245,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = {
> >  };
> >  
> >  static const struct ls_pcie_drvdata layerscape_drvdata = {
> > -	.pf_off = 0xc0000,
> > +	.pf_lut_off = 0xc0000,
> >  	.pm_support = true,
> >  	.exit_from_l2 = ls_pcie_exit_from_l2,
> >  };
> > @@ -295,7 +295,7 @@ static int ls_pcie_probe(struct platform_device *pdev)
> >  
> >  	pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");
> >  
> > -	pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off;
> > +	pcie->pf_lut_base = pci->dbi_base + pcie->drvdata->pf_lut_off;
> >  
> >  	if (pcie->drvdata->flags & LS_PCIE_DRV_SCFG) {
> >  
> > -- 
> > 2.34.1
> > 
> 
> -- 
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