Re: [PATCH net-next v4 2/2] net:dsa:microchip: add property to select

[Oleksij Rempel]

On Mon, Oct 23, 2023 at 10:22:30AM +0200, Ante Knezic wrote:
> On Mon, 23 Oct 2023 09:58:48 +0200, Oleksij Rempel wrote:
> 
> > If I see it correctly, KSZ9897R supports RMII on two ports (6 and 7)
> > with configurable clock direction. See page 124 "5.2.3.2 XMII Port Control 1
> > Register"
> > http://ww1.microchip.com/downloads/en/DeviceDoc/00002330B.pdf
> 
> Clock direction is possible I guess with other devices as well, but I don't see
> this specific property (routing REFCLKO to REFCLKI internally when switch is
> used as clock provider) for any other, including KSZ9897?
>
> I am no expert on micrel switches, but this to me looks like something specific
> only to KSZ88X3 devices as the clocking seems a bit different on KSZ9897 and
> alike. KSZ88X3 may generate clock to REFCLKO but still needs this clock fed
> back to REFCLKI (or will be routed internally with the "microchip-rmii-internal"
> property). This is managed differently on KSZ9897?

Here is KSZ8873 as initial reference:
https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/DataSheets/00002348A.pdf
3.3.9 RMII INTERFACE OPERATION:
"When EN_REFCLKO_3 is high, KSZ8873RLL will output a 50 MHz in REFCLKO_3.
Register 198 bit[3] is used to select internal or external reference
clock. Internal reference clock means that the clock for the RMII of
KSZ8873RLL will be provided by the KSZ8873RLL internally and the
REFCLKI_3 pin is unconnected. For the external reference clock, the
clock will provide to KSZ8873RLL via REFCLKI_3."

KSZ9897:
http://ww1.microchip.com/downloads/en/DeviceDoc/00002330B.pdf
4.11.2 REDUCED MEDIA INDEPENDENT INTERFACE (RMII)

"The user selects one of the two RMII clocking modes by setting the
appropriate strapping option. The clocking mode is selected separately
for ports 6 and 7.

While in RMII Normal Mode, the port will require an external 50MHz
signal to be input to TX_CLKx/REFCLKIx from an external source. This
mode is selected by strapping the appropriate pin (RXD6_1 for port 6;
RXD7_1 for port 7) high during reset.

While in RMII Clock Mode, the port will output a 50MHz clock on
RX_CLKx/REFCLKOx, which is derived from the 25MHz crystal or oscillator
attached to the XI clock input. The TX_CLKx/REFCLKIx input is unused in
this mode. This mode is selected by strapping the appropriate pin
(RXD6_1 for port 6; RXD7_1 for port 7) low during reset.
"

Information about corresponding bits I linked in previous email.

I do not see much differences.

Regards,
Oleksij
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