Re: [PATCH] x86/tdx: Override the tsc calibration for TDX VMs

[Vishal Annapurve]

On Sat, Oct 14, 2023 at 4:32 AM Sean Christopherson <seanjc@xxxxxxxxxx> wrote:
>
> On Fri, Oct 13, 2023, Sean Christopherson wrote:
> > On Fri, Oct 06, 2023, Vishal Annapurve wrote:
> > > TSC calibration for native execution gets the TSC frequency from CPUID,
> > > but also ends up setting lapic_timer_period. When using oneshot mode
> > > with lapic timer, predefined value of lapic_timer_period causes lapic
> > > timer calibration to be skipped with wrong multipliers set for lapic
> > > timer.
> > >
> > > To avoid this issue, override the TSC calibration step for TDX VMs to
> > > just calculate the TSC frequency using cpuid values.
> >
> > This is a hack to workaround a KVM TDX bug.  Per Intel's SDM:
> >
> >   The APIC timer frequency will be the processor’s bus clock or core crystal
> >   clock frequency (when TSC/core crystal clock ratio is enumerated in CPUID
> >   leaf 0x15) divided by the value specified in the divide configuration register.
> >
> > TDX hardcodes the core crystal frequency to 25Mhz, whereas KVM hardcodes the APIC
> > bus frequency to 1Ghz.  Upstream KVM's *current* behavior is fine, because KVM
> > doesn't advertise support for CPUID 0x15, i.e. doesn't announce to host userspace
> > that it's safe to expose CPUID 0x15 to the guest.  Because TDX makes exposing
> > CPUID 0x15 mandatory, KVM needs to be taught to correctly emulate the guest's
> > APIC bus frequency, a.k.a. the TDX guest core crystal frequency of 25Mhz.
> >

Ack, makes sense to pursue this fix from the KVM TDX side instead of
guest changes as per your suggestion.

>
>
> > I.e. tmict_to_ns() needs to replace APIC_BUS_CYCLE_NS with some math that makes
> > the guest's APIC timer actually run at 25Mhz given whatever the host APIC bus
> > runs at.
> >
> >   static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict)
> >   {
> >       return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count;
> >   }
>