[PATCH V2 3/5] arm64: zynqmp: Add ZynqnMP nvmem nodes

From: Praveen Teja Kundanala
Date: Thu Oct 19 2023 - 02:08:01 EST


Add nvmem DT nodes for ZynqMP SOC

Signed-off-by: Praveen Teja Kundanala <praveen.teja.kundanala@xxxxxxx>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 59 +++++++++++++++++++++++++-
1 file changed, 57 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index b61fc99cd911..b7433e6b9d6c 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -194,14 +194,69 @@ zynqmp_power: zynqmp-power {
mbox-names = "tx", "rx";
};

- nvmem_firmware {
+ nvmem-firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;

- soc_revision: soc_revision@0 {
+ soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
+ /* efuse access */
+ efuse_dna: efuse-dna@c {
+ reg = <0xc 0xc>;
+ };
+ efuse_usr0: efuse-usr0@20 {
+ reg = <0x20 0x4>;
+ };
+ efuse_usr1: efuse-usr1@24 {
+ reg = <0x24 0x4>;
+ };
+ efuse_usr2: efuse-usr2@28 {
+ reg = <0x28 0x4>;
+ };
+ efuse_usr3: efuse-usr3@2c {
+ reg = <0x2c 0x4>;
+ };
+ efuse_usr4: efuse-usr4@30 {
+ reg = <0x30 0x4>;
+ };
+ efuse_usr5: efuse-usr5@34 {
+ reg = <0x34 0x4>;
+ };
+ efuse_usr6: efuse-usr6@38 {
+ reg = <0x38 0x4>;
+ };
+ efuse_usr7: efuse-usr7@3c {
+ reg = <0x3c 0x4>;
+ };
+ efuse_miscusr: efuse-miscusr@40 {
+ reg = <0x40 0x4>;
+ };
+ efuse_chash: efuse-chash@50 {
+ reg = <0x50 0x4>;
+ };
+ efuse_pufmisc: efuse-pufmisc@54 {
+ reg = <0x54 0x4>;
+ };
+ efuse_sec: efuse-sec@58 {
+ reg = <0x58 0x4>;
+ };
+ efuse_spkid: efuse-spkid@5c {
+ reg = <0x5c 0x4>;
+ };
+ efuse_aeskey: efuse-aeskey@60 {
+ reg = <0x60 0x20>;
+ };
+ efuse_ppk0hash: efuse-ppk0hash@a0 {
+ reg = <0xa0 0x30>;
+ };
+ efuse_ppk1hash: efuse-ppk1hash@d0 {
+ reg = <0xd0 0x30>;
+ };
+ efuse_pufuser: efuse-pufuser@100 {
+ reg = <0x100 0x7F>;
+ };
};

zynqmp_pcap: pcap {
--
2.36.1