Re: [PATCH] PCI: keystone: Don't enable BAR0 if link is not detected

[Siddharth Vadapalli]

Hello,

On 17/10/23 02:59, Serge Semin wrote:
> Hi Siddharth
> 

...

>>>
>>> I assume MSI-X actually does work for downstream endpoints?  I
>>> wouldn't think anybody would have bothered with
>>> ks_pcie_v3_65_add_bus() unless MSI-X works.
>>
>> Yes, I think it is supposed to work, but it doesn't seem to be working right now
>> considering that even with Endpoint device connected, the readl() returns all Fs.
> 
> Could you please have look at what DW PCIe IP-core version is utilized
> in the Keystone PCIe host controller? If it's of v5.x then here is

The DW PCIe IP-core version is 4.90a.

> what HW databook says about the BARs initialization: "If you do use a
> BAR, then you should program it to capture TLPs that are targeted to
> your local non-application memory space residing on TRGT1, and not for
> the application on TRGT0 (dbi). The BAR range must be outside of the
> three Base/Limit regions."

Yes, it's the same even in the DW PCIe IP-core version 4.90a Databook:

3.5.7.2 RC Mode

Two BARs are present but are not expected to be used. You should disable them or
else they will be unnecessarily assigned memory during device enumeration. If
you do use a BAR, then you should program it to capture TLPs that are targeted
to your local non-application memory space residing on TRGT1, and not for the
application on TRGT1. The BAR range must be outside of the three Base/Limit regions.

> 
> I have no idea whether the BAR being set with an address within the
> Base/Limit regions could have caused the lags you see, but I would
> have at least checked that.

I will check that. Thank you for sharing your feedback.

> 
> -Serge(y)
> 
>>
>> -- 
>> Regards,
>> Siddharth.

-- 
Regards,
Siddharth.