[PATCH v3 06/11] dt-bindings: timer: Add Sophgo sg2042 CLINT timer

[Chen Wang]

From: Inochi Amaoto <inochiama@xxxxxxxxxxx>

The clint of Sophgo sg2042 is incompatible with the standard sifive
clint, as the timer and ipi device on the different address, and can
not be handled by the sifive,clint DT.

In addition, the timers of sg2042 are mapped by per cluster, which is
hard to merge with its ipi device.

To avoid conficts caused by using the same clint compatible string when
this device is parsed by SBI, add a new vendor specific compatible string
to identify the timer of sg2042 soc.

Signed-off-by: Inochi Amaoto <inochiama@xxxxxxxxxxx>
Signed-off-by: Chen Wang <wangchen20@xxxxxxxxxxx>
Signed-off-by: Chen Wang <unicornxw@xxxxxxxxx>
---
 .../timer/sophgo,sg2042-clint-mtimer.yaml     | 42 +++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml

diff --git a/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml b/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
new file mode 100644
index 000000000000..5da0947d048a
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/sophgo,sg2042-clint-mtimer.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/sophgo,sg2042-clint-mtimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CLINT Timer
+
+maintainers:
+  - Inochi Amaoto <inochiama@xxxxxxxxxxx>
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - const: sophgo,sg2042-clint-mtimer
+
+  reg:
+    maxItems: 1
+
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts-extended
+
+examples:
+  - |
+    timer@ac000000 {
+      compatible = "sophgo,sg2042-clint-mtimer";
+      interrupts-extended = <&cpu1intc 7>,
+                            <&cpu2intc 7>,
+                            <&cpu3intc 7>,
+                            <&cpu4intc 7>;
+      reg = <0xac000000 0x00010000>;
+    };
+...
-- 
2.25.1