Re: [PATCH v2 08/11] serial: 8250_dw: Add Sophgo SG2042 support

[Chen Wang]

Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx> 于2023年9月22日周五 18:40写道：
>
> Ben Dooks wrote:
> > On 20/09/2023 07:40, Chen Wang wrote:
> > > From: Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>
> > >
> > > Add quirk to skip setting the input clock rate for the uarts on the
> > > Sophgo SG2042 SoC similar to the StarFive JH7100.
> >
> > I'd love an actual explanation of why this is necessary here.
>
> Makes sense. For the JH7100 the commit message is:
>
>   On the StarFive JH7100 RISC-V SoC the UART core clocks can't be set to
>   exactly 16 * 115200Hz and many other common bitrates. Trying this will
>   only result in a higher input clock, but low enough that the UART's
>   internal divisor can't come close enough to the baud rate target.
>   So rather than try to set the input clock it's better to skip the
>   clk_set_rate call and rely solely on the UART's internal divisor.
>
> @Chen Wang is this also true for the SG2042?
>
> /Emil

Emil & Ben,
After double-checking with Sophgo engineers and doing more
investigation, we think the original changes(quirk to skip setting the
input clock) on UART may not  be required. Due to currently, the
target of this patchset is just to enable a minimal system and no
clock relateding changes are included yet. I will first remove this
quirk change on UART and use the fixed frequence - 500M - and reply
solely on the UART's internal divisor to work. We will re-evaluate
this quirk change in next patchset when we involve clock related
stuff.
Looping Haijiao, engineer from Sophgo, who is working on clock on sg2042.

Regards,
Chen