RE: [PATCH 1/1] dmaengine: fsl-edma: fix edma4 channel enable failure on second attempt

[Frank Li]

> -----Original Message-----
> From: Frank Li <frank.li@xxxxxxx>
> Sent: Wednesday, August 23, 2023 1:27 PM
> To: vkoul@xxxxxxxxxx
> Cc: devicetree@xxxxxxxxxxxxxxx; dmaengine@xxxxxxxxxxxxxxx; Frank Li
> <frank.li@xxxxxxx>; imx@xxxxxxxxxxxxxxx; Joy Zou <joy.zou@xxxxxxx>;
> krzysztof.kozlowski+dt@xxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Peng Fan
> <peng.fan@xxxxxxx>; robh+dt@xxxxxxxxxx; Shenwei Wang
> <shenwei.wang@xxxxxxx>
> Subject: [PATCH 1/1] dmaengine: fsl-edma: fix edma4 channel enable failure
> on second attempt
> 
> When attempting to start DMA for the second time using
> fsl_edma3_enable_request(), channel never start.
> 
> CHn_MUX must have a unique value when selecting a peripheral slot in the
> channel mux configuration. The only value that may overlap is source 0.
> If there is an attempt to write a mux configuration value that is already
> consumed by another channel, a mux configuration of 0 (SRC = 0) will be
> written.
> 
> Check CHn_MUX before writing in fsl_edma3_enable_request().
> 
> Fixes: 72f5801a4e2b ("dmaengine: fsl-edma: integrate v3 support")
> Signed-off-by: Frank Li <Frank.Li@xxxxxxx>
> ---

@vinod: 
	ping 

>  drivers/dma/fsl-edma-common.c | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-
> common.c
> index a0f5741abcc4..edb92fa93315 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -92,8 +92,14 @@ static void fsl_edma3_enable_request(struct
> fsl_edma_chan *fsl_chan)
> 
>  	edma_writel_chreg(fsl_chan, val, ch_sbr);
> 
> -	if (flags & FSL_EDMA_DRV_HAS_CHMUX)
> -		edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux);
> +	if (flags & FSL_EDMA_DRV_HAS_CHMUX) {
> +		/*
> +		 * ch_mux: With the exception of 0, attempts to write a value
> +		 * already in use will be forced to 0.
> +		 */
> +		if (!edma_readl_chreg(fsl_chan, ch_mux))
> +			edma_writel_chreg(fsl_chan, fsl_chan->srcid,
> ch_mux);
> +	}
> 
>  	val = edma_readl_chreg(fsl_chan, ch_csr);
>  	val |= EDMA_V3_CH_CSR_ERQ;
> --
> 2.34.1