Re: [PATCH v1 3/3] PCI: qcom: Add OPP suuport for speed based performance state of RPMH

From: kernel test robot
Date: Tue Aug 15 2023 - 10:04:51 EST


Hi Krishna,

kernel test robot noticed the following build warnings:

[auto build test WARNING on pci/for-linus]
[also build test WARNING on robh/for-next linus/master v6.5-rc6 next-20230809]
[cannot apply to pci/next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Krishna-chaitanya-chundru/dt-bindings-pci-qcom-Add-binding-for-operating-points-v2/20230815-203103
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git for-linus
patch link: https://lore.kernel.org/r/1692102408-7010-4-git-send-email-quic_krichai%40quicinc.com
patch subject: [PATCH v1 3/3] PCI: qcom: Add OPP suuport for speed based performance state of RPMH
config: loongarch-allyesconfig (https://download.01.org/0day-ci/archive/20230815/202308152125.sU1aQfAd-lkp@xxxxxxxxx/config)
compiler: loongarch64-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230815/202308152125.sU1aQfAd-lkp@xxxxxxxxx/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202308152125.sU1aQfAd-lkp@xxxxxxxxx/

All warnings (new ones prefixed by >>):

drivers/pci/controller/dwc/pcie-qcom.c: In function 'qcom_pcie_opp_update':
>> drivers/pci/controller/dwc/pcie-qcom.c:1368:13: warning: variable 'ret' set but not used [-Wunused-but-set-variable]
1368 | int ret = 0;
| ^~~


vim +/ret +1368 drivers/pci/controller/dwc/pcie-qcom.c

1360
1361 static void qcom_pcie_opp_update(struct qcom_pcie *pcie)
1362 {
1363 struct dw_pcie *pci = pcie->pci;
1364 struct dev_pm_opp *opp;
1365 u32 offset, status;
1366 uint32_t freq;
1367 int speed;
> 1368 int ret = 0;
1369
1370 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1371 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1372
1373 /* Only update constraints if link is up. */
1374 if (!(status & PCI_EXP_LNKSTA_DLLLA))
1375 return;
1376
1377 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
1378
1379 switch (speed) {
1380 case 1:
1381 freq = 2500000;
1382 break;
1383 case 2:
1384 freq = 5000000;
1385 break;
1386 case 3:
1387 freq = 8000000;
1388 break;
1389 default:
1390 WARN_ON_ONCE(1);
1391 fallthrough;
1392 case 4:
1393 freq = 16000000;
1394 break;
1395 }
1396
1397 opp = dev_pm_opp_find_freq_exact(pci->dev, freq, true);
1398
1399 if (!IS_ERR(opp)) {
1400 ret = dev_pm_opp_get_voltage(opp);
1401 dev_pm_opp_put(opp);
1402 }
1403

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