Re: [RFC PATCH] membarrier: riscv: Provide core serializing command

From: Andrea Parri
Date: Fri Aug 04 2023 - 10:59:36 EST

> What is the relationship between FENCE.I and instruction cache flush on
> RISC-V ?

The exact nature of this relationship is implementation-dependent. From
commentary included in the ISA portion referred to in the changelog:

A simple implementation can flush the local instruction cache and
the instruction pipeline when the FENCE.I is executed. A more
complex implementation might snoop the instruction (data) cache on
every data (instruction) cache miss, or use an inclusive unified
private L2 cache to invalidate lines from the primary instruction
cache when they are being written by a local store instruction. If
instruction and data caches are kept coherent in this way, or if
the memory system consists of only uncached RAMs, then just the
fetch pipeline needs to be flushed at a FENCE.I. [..]

Mmh, does this help?