Re: [RFC PATCH] membarrier: riscv: Provide core serializing command

From: Mathieu Desnoyers
Date: Fri Aug 04 2023 - 10:19:34 EST

On 8/3/23 20:16, Andrea Parri wrote:
Can you double-check that riscv switch_mm() implies a fence.i or equivalent
on the CPU doing the switch_mm ?

AFAICT, (riscv) switch_mm() does not guarantee that.

AFAIR membarrier use of sync_core_before_usermode relies on switch_mm
issuing a core serializing instruction.

I see. Thanks for the clarification.

BTW, the comment in __schedule() suggests that membarrier also relies on
switch_mm() issuing a full memory barrier: I don't think this holds.

Removing the "deferred icache flush" logic in switch_mm() - in favour of
a "plain" MB; FENCE.I - would meet both of these requirements.

What is the relationship between FENCE.I and instruction cache flush on RISC-V ?

On other architectures, there is need for careful flushing of the instruction cache for the address range that was modified, _and_ to issue a core serializing instruction on all cores (this last part being performed by membarrier SYNC_CORE) between the point where the old instructions were executed and before the new instructions are executed.



Other ideas?


Mathieu Desnoyers
EfficiOS Inc.