[PATCH] ARM: dts: microchip: split interrupts per cells
From: Krzysztof Kozlowski
Date: Sun Jul 30 2023 - 07:15:55 EST
Each interrupt should be in its own cell. This is much more readable.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
---
arch/arm/boot/dts/microchip/at91rm9200.dtsi | 12 +++---
arch/arm/boot/dts/microchip/at91sam9260.dtsi | 12 +++---
arch/arm/boot/dts/microchip/sama5d2.dtsi | 6 +--
arch/arm/boot/dts/microchip/sama7g5.dtsi | 40 ++++++++++----------
4 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/arch/arm/boot/dts/microchip/at91rm9200.dtsi b/arch/arm/boot/dts/microchip/at91rm9200.dtsi
index 37b500f6f395..16c675e3a890 100644
--- a/arch/arm/boot/dts/microchip/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/microchip/at91rm9200.dtsi
@@ -135,9 +135,9 @@ tcb0: timer@fffa0000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa0000 0x100>;
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
- 18 IRQ_TYPE_LEVEL_HIGH 0
- 19 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
+ <18 IRQ_TYPE_LEVEL_HIGH 0>,
+ <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -147,9 +147,9 @@ tcb1: timer@fffa4000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa4000 0x100>;
- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
- 21 IRQ_TYPE_LEVEL_HIGH 0
- 22 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>,
+ <21 IRQ_TYPE_LEVEL_HIGH 0>,
+ <22 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
diff --git a/arch/arm/boot/dts/microchip/at91sam9260.dtsi b/arch/arm/boot/dts/microchip/at91sam9260.dtsi
index 27b4a21f13c1..e56d5546554c 100644
--- a/arch/arm/boot/dts/microchip/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/microchip/at91sam9260.dtsi
@@ -148,9 +148,9 @@ tcb0: timer@fffa0000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffa0000 0x100>;
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
- 18 IRQ_TYPE_LEVEL_HIGH 0
- 19 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
+ <18 IRQ_TYPE_LEVEL_HIGH 0>,
+ <19 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
@@ -160,9 +160,9 @@ tcb1: timer@fffdc000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffdc000 0x100>;
- interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
- 27 IRQ_TYPE_LEVEL_HIGH 0
- 28 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>,
+ <27 IRQ_TYPE_LEVEL_HIGH 0>,
+ <28 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
diff --git a/arch/arm/boot/dts/microchip/sama5d2.dtsi b/arch/arm/boot/dts/microchip/sama5d2.dtsi
index daeeb24e5f4d..5f8e297e19ed 100644
--- a/arch/arm/boot/dts/microchip/sama5d2.dtsi
+++ b/arch/arm/boot/dts/microchip/sama5d2.dtsi
@@ -382,9 +382,9 @@ AT91_XDMAC_DT_PERID(21))>,
macb0: ethernet@f8008000 {
compatible = "atmel,sama5d2-gem";
reg = <0xf8008000 0x1000>;
- interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
- 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
- 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */
+ <66 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */
+ <67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
clock-names = "hclk", "pclk";
status = "disabled";
diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi
index 9642a42d84e6..269e0a3ca269 100644
--- a/arch/arm/boot/dts/microchip/sama7g5.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi
@@ -366,8 +366,8 @@ can0: can@e0828000 {
compatible = "bosch,m_can";
reg = <0xe0828000 0x100>, <0x100000 0x7800>;
reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
clock-names = "hclk", "cclk";
@@ -382,8 +382,8 @@ can1: can@e082c000 {
compatible = "bosch,m_can";
reg = <0xe082c000 0x100>, <0x100000 0xbc00>;
reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
clock-names = "hclk", "cclk";
@@ -398,8 +398,8 @@ can2: can@e0830000 {
compatible = "bosch,m_can";
reg = <0xe0830000 0x100>, <0x100000 0x10000>;
reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>;
clock-names = "hclk", "cclk";
@@ -414,8 +414,8 @@ can3: can@e0834000 {
compatible = "bosch,m_can";
reg = <0xe0834000 0x100>, <0x110000 0x4400>;
reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>;
clock-names = "hclk", "cclk";
@@ -430,8 +430,8 @@ can4: can@e0838000 {
compatible = "bosch,m_can";
reg = <0xe0838000 0x100>, <0x110000 0x8800>;
reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>;
clock-names = "hclk", "cclk";
@@ -446,8 +446,8 @@ can5: can@e083c000 {
compatible = "bosch,m_can";
reg = <0xe083c000 0x100>, <0x110000 0xcc00>;
reg-names = "m_can", "message_ram";
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
clock-names = "hclk", "cclk";
@@ -845,12 +845,12 @@ uart7: serial@200 {
gmac0: ethernet@e2800000 {
compatible = "microchip,sama7g5-gem";
reg = <0xe2800000 0x1000>;
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>;
clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
@@ -861,8 +861,8 @@ GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH
gmac1: ethernet@e2804000 {
compatible = "microchip,sama7g5-emac";
reg = <0xe2804000 0x1000>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
- GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
clock-names = "pclk", "hclk";
status = "disabled";
--
2.34.1