Re: [PATCH v3 0/8] Add Sipeed Lichee Pi 4A RISC-V board support

[Xi Ruoyao]

On Tue, 2023-07-25 at 08:52 +0100, Conor Dooley wrote:
> Are you using the vendor OpenSBI? IIRC, and the lads can probably
> correct me here, you need to have an OpenSBI that contains
> https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6
> which the vendor supplied OpenSBI does not have.

I'll try OpenSBI from the upstream.

> > And this line
> > 
> > Memory: 8145304K/8388608K available (4922K kernel code, 4786K rwdata, 2048K rodata, 2148K init, 393K bss, 243304K reserved, 0K cma-reserved)
> > 
> > does not match my hardware (my board is a 16 GB DRAM variant).  So in
> > the future we'll need multiple DTs for all the variants?
> 
> A bootloader stage would ideally patch the DT that the kernel ends up
> getting. If you're loading your own dtb, you can do it easily in U-Boot
> after you extract it from your FIT image or whatever. I have no idea
> what the vendor U-Boot does.

The vendor ships three DTs and in uboot there are some fancy logic to
detect which should be used.