Re: [PATCH v2 1/2] arm64: dts: ti: Use local header for SERDES MUX idle-state values

From: Peter Rosin
Date: Sat Jul 22 2023 - 06:15:44 EST

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In reply to: Jayesh Choudhary: "[PATCH v2 1/2] arm64: dts: ti: Use local header for SERDES MUX idle-state values"
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Hi!

2023-07-21 at 14:57, Jayesh Choudhary wrote:
> The DTS uses constants for SERDES MUX idle state values which were earlier
> provided as bindings header. But they are unsuitable for bindings.
> So move these constants in a header next to DTS.
>
> Also add J784S4 SERDES4 lane definitions which were missed earlier.
>
> Suggested-by: Nishanth Menon <nm@xxxxxx>
> Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> Suggested-by: Roger Quadros <rogerq@xxxxxxxxxx>
> Link: https://lore.kernel.org/linux-arm-kernel/b24c2124-fe3b-246c-9af9-3ecee9fb32d4@xxxxxxxxxx/
> Signed-off-by: Jayesh Choudhary <j-choudhary@xxxxxx>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> Acked-by: Roger Quadros <rogerq@xxxxxxxxxx>

Thanks for getting these constants out of my hair :-)

I assume the patches will take some other route to Linus than by me?

Acked-by: Peter Rosin <peda@xxxxxxxxxx>

Cheers,
Peter

> ---
> arch/arm64/boot/dts/ti/k3-am642-evm.dts | 3 +-
> .../dts/ti/k3-am642-phyboard-electra-rdk.dts | 3 +-
> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 3 +-
> .../boot/dts/ti/k3-am68-sk-base-board.dts | 3 +-
> .../dts/ti/k3-j7200-common-proc-board.dts | 3 +-
> .../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 2 +-
> .../ti/k3-j721e-evm-quad-port-eth-exp.dtso | 2 +-
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 3 +-
> .../dts/ti/k3-j721s2-common-proc-board.dts | 3 +-
> arch/arm64/boot/dts/ti/k3-serdes.h | 204 ++++++++++++++++++
> 10 files changed, 220 insertions(+), 9 deletions(-)
> create mode 100644 arch/arm64/boot/dts/ti/k3-serdes.h
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 15c282c93467..d84e7ee16032 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -6,12 +6,13 @@
> /dts-v1/;
>
> #include <dt-bindings/phy/phy.h>
> -#include <dt-bindings/mux/ti-serdes.h>
> #include <dt-bindings/leds/common.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/net/ti-dp83867.h>
> #include "k3-am642.dtsi"
>
> +#include "k3-serdes.h"
> +
> / {
> compatible = "ti,am642-evm", "ti,am642";
> model = "Texas Instruments AM642 EVM";
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
> index 9c418abd29d8..9175e96842d8 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts
> @@ -16,11 +16,12 @@
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/leds/common.h>
> #include <dt-bindings/leds/leds-pca9532.h>
> -#include <dt-bindings/mux/ti-serdes.h>
> #include <dt-bindings/phy/phy.h>
> #include "k3-am642.dtsi"
> #include "k3-am64-phycore-som.dtsi"
>
> +#include "k3-serdes.h"
> +
> / {
> compatible = "phytec,am642-phyboard-electra-rdk",
> "phytec,am64-phycore-som", "ti,am642";
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> index cbce43dbe3f9..963d796a3a97 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> @@ -5,13 +5,14 @@
>
> /dts-v1/;
>
> -#include <dt-bindings/mux/ti-serdes.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/net/ti-dp83867.h>
> #include <dt-bindings/leds/common.h>
> #include "k3-am642.dtsi"
>
> +#include "k3-serdes.h"
> +
> / {
> compatible = "ti,am642-sk", "ti,am642";
> model = "Texas Instruments AM642 SK";
> diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
> index d5889ba3fa46..21ad49cfa7ee 100644
> --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
> @@ -11,7 +11,8 @@
> #include <dt-bindings/net/ti-dp83867.h>
> #include <dt-bindings/phy/phy-cadence.h>
> #include <dt-bindings/phy/phy.h>
> -#include <dt-bindings/mux/ti-serdes.h>
> +
> +#include "k3-serdes.h"
>
> / {
> compatible = "ti,am68-sk", "ti,j721s2";
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index 3cf288128c3f..92a541491172 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -8,9 +8,10 @@
> #include "k3-j7200-som-p0.dtsi"
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/net/ti-dp83867.h>
> -#include <dt-bindings/mux/ti-serdes.h>
> #include <dt-bindings/phy/phy.h>
>
> +#include "k3-serdes.h"
> +
> / {
> compatible = "ti,j7200-evm", "ti,j7200";
> model = "Texas Instruments J7200 EVM";
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
> index 34a0747cbe69..32d905235ed7 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
> @@ -10,9 +10,9 @@
> /plugin/;
>
> #include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/mux/ti-serdes.h>
>
> #include "k3-pinctrl.h"
> +#include "k3-serdes.h"
>
> &{/} {
> aliases {
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
> index 6f0adf591b98..d4c51ffc3d6b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
> @@ -10,11 +10,11 @@
> /plugin/;
>
> #include <dt-bindings/gpio/gpio.h>
> -#include <dt-bindings/mux/ti-serdes.h>
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/phy/phy-cadence.h>
>
> #include "k3-pinctrl.h"
> +#include "k3-serdes.h"
>
> &{/} {
> aliases {
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index 6c9fe28b6de7..3acd55ffd4ff 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -7,7 +7,8 @@
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/phy/phy-ti.h>
> #include <dt-bindings/mux/mux.h>
> -#include <dt-bindings/mux/ti-serdes.h>
> +
> +#include "k3-serdes.h"
>
> / {
> cmn_refclk: clock-cmnrefclk {
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> index 092ab1e14ba5..02b7a559bdf2 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> @@ -11,7 +11,8 @@
> #include <dt-bindings/net/ti-dp83867.h>
> #include <dt-bindings/phy/phy-cadence.h>
> #include <dt-bindings/phy/phy.h>
> -#include <dt-bindings/mux/ti-serdes.h>
> +
> +#include "k3-serdes.h"
>
> / {
> compatible = "ti,j721s2-evm", "ti,j721s2";
> diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
> new file mode 100644
> index 000000000000..29167f85c1f6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-serdes.h
> @@ -0,0 +1,204 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for SERDES MUX for TI SoCs
> + *
> + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef DTS_ARM64_TI_K3_SERDES_H
> +#define DTS_ARM64_TI_K3_SERDES_H
> +
> +/* J721E */
> +
> +#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0
> +#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1
> +#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2
> +#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3
> +
> +#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0
> +#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1
> +#define J721E_SERDES0_LANE1_USB3_0 0x2
> +#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3
> +
> +#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0
> +#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1
> +#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2
> +#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3
> +
> +#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0
> +#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1
> +#define J721E_SERDES1_LANE1_USB3_1 0x2
> +#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3
> +
> +#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0
> +#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1
> +#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2
> +#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3
> +
> +#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0
> +#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1
> +#define J721E_SERDES2_LANE1_USB3_1 0x2
> +#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3
> +
> +#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0
> +#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1
> +#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2
> +#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3
> +
> +#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0
> +#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1
> +#define J721E_SERDES3_LANE1_USB3_0 0x2
> +#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3
> +
> +#define J721E_SERDES4_LANE0_EDP_LANE0 0x0
> +#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1
> +#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2
> +#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3
> +
> +#define J721E_SERDES4_LANE1_EDP_LANE1 0x0
> +#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1
> +#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2
> +#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3
> +
> +#define J721E_SERDES4_LANE2_EDP_LANE2 0x0
> +#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1
> +#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2
> +#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3
> +
> +#define J721E_SERDES4_LANE3_EDP_LANE3 0x0
> +#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1
> +#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2
> +#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3
> +
> +/* J7200 */
> +
> +#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0
> +#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1
> +#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2
> +#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3
> +
> +#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0
> +#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1
> +#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2
> +#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3
> +
> +#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0
> +#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1
> +#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2
> +#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3
> +
> +#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0
> +#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1
> +#define J7200_SERDES0_LANE3_USB 0x2
> +#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3
> +
> +/* AM64 */
> +
> +#define AM64_SERDES0_LANE0_PCIE0 0x0
> +#define AM64_SERDES0_LANE0_USB 0x1
> +
> +/* J721S2 */
> +
> +#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0
> +#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1
> +#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2
> +#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3
> +
> +#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0
> +#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1
> +#define J721S2_SERDES0_LANE1_USB 0x2
> +#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3
> +
> +#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
> +#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
> +#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
> +#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
> +
> +#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0
> +#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1
> +#define J721S2_SERDES0_LANE3_USB 0x2
> +#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3
> +
> +/* J784S4 */
> +
> +#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0
> +#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1
> +#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2
> +#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0
> +#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1
> +#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2
> +#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0
> +#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1
> +#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2
> +#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0
> +#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1
> +#define J784S4_SERDES0_LANE3_USB 0x2
> +#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0
> +#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1
> +#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2
> +#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0
> +#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1
> +#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2
> +#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0
> +#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1
> +#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2
> +#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0
> +#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1
> +#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2
> +#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0
> +#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1
> +#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2
> +#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0
> +#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1
> +#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2
> +#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0
> +#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1
> +#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2
> +#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0
> +#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1
> +#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2
> +#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES4_LANE0_EDP_LANE0 0x0
> +#define J784S4_SERDES4_LANE0_QSGMII_LANE5 0x1
> +#define J784S4_SERDES4_LANE0_IP3_UNUSED 0x2
> +#define J784S4_SERDES4_LANE0_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES4_LANE1_EDP_LANE1 0x0
> +#define J784S4_SERDES4_LANE1_QSGMII_LANE6 0x1
> +#define J784S4_SERDES4_LANE1_IP3_UNUSED 0x2
> +#define J784S4_SERDES4_LANE1_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES4_LANE2_EDP_LANE2 0x0
> +#define J784S4_SERDES4_LANE2_QSGMII_LANE7 0x1
> +#define J784S4_SERDES4_LANE2_IP3_UNUSED 0x2
> +#define J784S4_SERDES4_LANE2_IP4_UNUSED 0x3
> +
> +#define J784S4_SERDES4_LANE3_EDP_LANE3 0x0
> +#define J784S4_SERDES4_LANE3_QSGMII_LANE8 0x1
> +#define J784S4_SERDES4_LANE3_USB 0x2
> +#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
> +
> +#endif /* DTS_ARM64_TI_K3_SERDES_H */

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