[PATCH 05/10] dt-bindings: clock: Add Marvell PXA1908 clock bindings
From: Duje Mihanović
Date: Fri Jul 21 2023 - 17:12:11 EST
Add the dt bindings for Marvell PXA1908 clock controller.
Signed-off-by: Duje Mihanović <duje.mihanovic@xxxxxxxx>
---
include/dt-bindings/clock/marvell,pxa1908.h | 93 +++++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h
diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h
new file mode 100644
index 000000000000..da9c5d499ae4
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,pxa1908.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __DTS_MARVELL_PXA1908_CLOCK_H
+#define __DTS_MARVELL_PXA1908_CLOCK_H
+
+/* plls */
+#define PXA1908_CLK_CLK32 0x1
+#define PXA1908_CLK_VCTCXO 0x2
+#define PXA1908_CLK_PLL1_624 0x3
+#define PXA1908_CLK_PLL1_416 0x4
+#define PXA1908_CLK_PLL1_499 0x5
+#define PXA1908_CLK_PLL1_832 0x6
+#define PXA1908_CLK_PLL1_1248 0x7
+#define PXA1908_CLK_PLL1_D2 0x8
+#define PXA1908_CLK_PLL1_D4 0x9
+#define PXA1908_CLK_PLL1_D8 0xa
+#define PXA1908_CLK_PLL1_D16 0xb
+#define PXA1908_CLK_PLL1_D6 0xc
+#define PXA1908_CLK_PLL1_D12 0xd
+#define PXA1908_CLK_PLL1_D24 0xe
+#define PXA1908_CLK_PLL1_D48 0xf
+#define PXA1908_CLK_PLL1_D96 0x10
+#define PXA1908_CLK_PLL1_D13 0x11
+#define PXA1908_CLK_PLL1_32 0x12
+#define PXA1908_CLK_PLL1_208 0x13
+#define PXA1908_CLK_PLL1_117 0x14
+#define PXA1908_CLK_PLL1_416_GATE 0x15
+#define PXA1908_CLK_PLL1_624_GATE 0x16
+#define PXA1908_CLK_PLL1_832_GATE 0x17
+#define PXA1908_CLK_PLL1_1248_GATE 0x18
+#define PXA1908_CLK_PLL1_D2_GATE 0x19
+#define PXA1908_CLK_PLL1_499_EN 0x1a
+#define PXA1908_CLK_PLL2VCO 0x1b
+#define PXA1908_CLK_PLL2 0x1c
+#define PXA1908_CLK_PLL2P 0x1d
+#define PXA1908_CLK_PLL2VCODIV3 0x1e
+#define PXA1908_CLK_PLL3VCO 0x1f
+#define PXA1908_CLK_PLL3 0x20
+#define PXA1908_CLK_PLL3P 0x21
+#define PXA1908_CLK_PLL3VCODIV3 0x22
+#define PXA1908_CLK_PLL4VCO 0x23
+#define PXA1908_CLK_PLL4 0x24
+#define PXA1908_CLK_PLL4P 0x25
+#define PXA1908_CLK_PLL4VCODIV3 0x26
+#define PXA1908_MPMU_NR_CLKS 38
+
+/* apb (apbc) peripherals */
+#define PXA1908_CLK_UART0 0x1
+#define PXA1908_CLK_UART1 0x2
+#define PXA1908_CLK_GPIO 0x3
+#define PXA1908_CLK_PWM0 0x4
+#define PXA1908_CLK_PWM1 0x5
+#define PXA1908_CLK_PWM2 0x6
+#define PXA1908_CLK_PWM3 0x7
+#define PXA1908_CLK_SSP0 0x8
+#define PXA1908_CLK_SSP1 0x9
+#define PXA1908_CLK_IPC_RST 0xa
+#define PXA1908_CLK_RTC 0xb
+#define PXA1908_CLK_TWSI0 0xc
+#define PXA1908_CLK_KPC 0xd
+#define PXA1908_CLK_SWJTAG 0x11
+#define PXA1908_CLK_SSP2 0x14
+#define PXA1908_CLK_TWSI1 0x19
+#define PXA1908_CLK_THERMAL 0x1c
+#define PXA1908_CLK_TWSI3 0x1d
+#define PXA1908_APBC_NR_CLKS 0x30
+
+/* apb (apbcp) peripherals */
+#define PXA1908_CLK_UART2 0x7
+#define PXA1908_CLK_TWSI2 0xa
+#define PXA1908_CLK_AICER 0xe
+#define PXA1908_APBCP_NR_CLKS 0xe
+
+/* axi (apmu) peripherals */
+#define PXA1908_CLK_CCIC1 0x9
+#define PXA1908_CLK_ISP 0xe
+#define PXA1908_CLK_GATE_CTRL 0x10
+#define PXA1908_CLK_DSI1 0x11
+#define PXA1908_CLK_DISP1 0x13
+#define PXA1908_CLK_CCIC0 0x14
+#define PXA1908_CLK_SDH0 0x15
+#define PXA1908_CLK_SDH1 0x16
+#define PXA1908_CLK_SDH2 0x38
+#define PXA1908_CLK_USB 0x17
+#define PXA1908_CLK_NF 0x18
+#define PXA1908_CLK_CORE_DEBUG 0x24
+#define PXA1908_CLK_VPU 0x29
+#define PXA1908_CLK_GC 0x51
+#define PXA1908_CLK_GC2D 0x3d
+#define PXA1908_CLK_TRACE 0x42
+#define PXA1908_CLK_DVC_DFC_DEBUG 0x50
+#define PXA1908_APMU_NR_CLKS 0x60
+
+#endif
--
2.41.0