Re: [PATCH v3 3/5] mmu_notifiers: Call invalidate_range() when invalidating TLBs

From: Catalin Marinas
Date: Fri Jul 21 2023 - 14:25:42 EST


On Thu, Jul 20, 2023 at 06:39:25PM +1000, Alistair Popple wrote:
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index 3456866..a99349d 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -13,6 +13,7 @@
> #include <linux/bitfield.h>
> #include <linux/mm_types.h>
> #include <linux/sched.h>
> +#include <linux/mmu_notifier.h>
> #include <asm/cputype.h>
> #include <asm/mmu.h>
>
> @@ -252,6 +253,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
> __tlbi(aside1is, asid);
> __tlbi_user(aside1is, asid);
> dsb(ish);
> + mmu_notifier_invalidate_range(mm, 0, -1UL);
> }
>
> static inline void __flush_tlb_page_nosync(struct mm_struct *mm,
> @@ -263,6 +265,8 @@ static inline void __flush_tlb_page_nosync(struct mm_struct *mm,
> addr = __TLBI_VADDR(uaddr, ASID(mm));
> __tlbi(vale1is, addr);
> __tlbi_user(vale1is, addr);
> + mmu_notifier_invalidate_range(mm, uaddr & PAGE_MASK,
> + (uaddr & PAGE_MASK) + PAGE_SIZE);

Nitpick: we have PAGE_ALIGN() for this.

For arm64:

Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx>