Re: [PATCH v4 1/2] PCI: dwc: Implement general suspend/resume functionality for L2/L3 transitions

[kernel test robot]

Hi Frank,

kernel test robot noticed the following build warnings:

[auto build test WARNING on v6.4]
[also build test WARNING on linus/master next-20230721]
[cannot apply to pci/next pci/for-linus v6.5-rc2 v6.5-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Frank-Li/PCI-layerscape-Add-power-management-support-for-ls1028a/20230721-051152
base:   v6.4
patch link:    https://lore.kernel.org/r/20230720210914.2030897-1-Frank.Li%40nxp.com
patch subject: [PATCH v4 1/2] PCI: dwc: Implement general suspend/resume functionality for L2/L3 transitions
config: mips-randconfig-r093-20230720 (https://download.01.org/0day-ci/archive/20230721/202307211904.zExw4Q8H-lkp@xxxxxxxxx/config)
compiler: mips64-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230721/202307211904.zExw4Q8H-lkp@xxxxxxxxx/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@xxxxxxxxx>
| Closes: https://lore.kernel.org/oe-kbuild-all/202307211904.zExw4Q8H-lkp@xxxxxxxxx/

sparse warnings: (new ones prefixed by >>)
>> drivers/pci/controller/dwc/pcie-designware-host.c:824:13: sparse: sparse: invalid assignment: |=
>> drivers/pci/controller/dwc/pcie-designware-host.c:824:13: sparse:    left side has type unsigned int
>> drivers/pci/controller/dwc/pcie-designware-host.c:824:13: sparse:    right side has type restricted pci_power_t

vim +824 drivers/pci/controller/dwc/pcie-designware-host.c

   811	
   812	/*
   813	 * This resemble the pci_set_power_state() interfaces, but these are for
   814	 * configuring host controllers, which are bridges *to* PCI devices but
   815	 * are not PCI devices themselves.
   816	 */
   817	static void dw_pcie_set_dstate(struct dw_pcie *pci, pci_power_t dstate)
   818	{
   819		u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_PM);
   820		u32 val;
   821	
   822		val = dw_pcie_readw_dbi(pci, offset + PCI_PM_CTRL);
   823		val &= ~PCI_PM_CTRL_STATE_MASK;
 > 824		val |= dstate;
   825		dw_pcie_writew_dbi(pci, offset + PCI_PM_CTRL, val);
   826	}
   827	

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