Re: [PATCH 1/5] arm64: dts: qcom: Add base SM4450 DTSI

[Tengfei Fan]

在 7/20/2023 3:54 PM, Konrad Dybcio 写道:
> On 19.07.2023 12:01, Tengfei Fan wrote:
> > This add based DTSI for SM4450 SoC and includes base description of
> > CPUs and interrupt-controller which helps to boot to shell with
> > console on boards with this SoC.
> >
> > Signed-off-by: Tengfei Fan <quic_tengfan@xxxxxxxxxxx>
> > ---
> [...]
>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/gpio/gpio.h>
> Please sort them alphabetically
V2 patch will resort them.
> > +
> > +/ {
> > +	interrupt-parent = <&intc>;
> > +
> [...]
>
> > +	cpus {
> > +		#address-cells = <2>;
> > +		#size-cells = <0>;
> > +
> > +		CPU0: cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "qcom,kryo";
> Please post dmesg | grep '\[', this is probably a standard ARM core.
sure, will do and update this compatible.
> > +			reg = <0x0 0x0>;
> > +			enable-method = "psci";
> > +			next-level-cache = <&L2_0>;
> > +			power-domains = <&CPU_PD0>;
> > +			power-domain-names = "psci";
> > +			#cooling-cells = <2>;
> > +			L2_0: l2-cache {
> Missing a newline before subnodes
V2 patch will add newline.
> > +				compatible = "cache";
> > +				cache-level = <2>;
> > +				cache-unified;
> > +				next-level-cache = <&L3_0>;
> > +				L3_0: l3-cache {
> Ditto
V2 patch will add newline.
> > +					compatible = "cache";
> > +					cache-level = <3>;
> > +					cache-unified;
> > +				};
> > +			};
> > +		};
> [...]
>
> > +
> > +		intc: interrupt-controller@17200000 {
> > +			compatible = "arm,gic-v3";
> > +			#interrupt-cells = <3>;
> > +			interrupt-controller;
> > +			#redistributor-regions = <1>;
> > +			redistributor-stride = <0x0 0x20000>;
> > +			reg = <0x0 0x17200000 0x0 0x10000>,     /* GICD */
> > +				<0x0 0x17260000 0x0 0x100000>;    /* GICR * 8 */
> Misasligned
V2 patch will align.
> also, please move reg and interrupts after compatible
V2 patch will resort.
> > +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> > +		};
> > +
> > +		timer@17420000 {
> > +			compatible = "arm,armv7-timer-mem";
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges = <0 0 0 0x20000000>;
> > +			reg = <0x0 0x17420000 0x0 0x1000>;
> > +			clock-frequency = <19200000>;
> Drop clock-frequency
V2 patch will Drop this clock-frequency node.
> [...]
>
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> > +				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> Misaligned
V2 patch will align.
> > +		clock-frequency = <19200000>;
> Drop
V2 patch will drop.
> Konrad
> > +	};
> > +};

--
Thx and BRs,
Tengfei Fan