Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

From: Liviu Dudau
Date: Tue Jul 18 2023 - 11:18:37 EST

On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> Add both PCIe3 controllers together with the shared PHY.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
> 1 file changed, 120 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> index 88d702575db2..8f210f002fac 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> @@ -7,6 +7,11 @@
> #include "rk3588-pinctrl.dtsi"
>
> / {
> + pcie30_phy_grf: syscon@fd5b8000 {
> + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> + reg = <0x0 0xfd5b8000 0x0 0x10000>;
> + };
> +
> pipe_phy1_grf: syscon@fd5c0000 {
> compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> reg = <0x0 0xfd5c0000 0x0 0x100>;

Hi Sebastian,

What tree is based this on? Even after applying your PCIe2 series I don't have the above
node so the patch doesn't apply to mainline.

Best regards,
Liviu


> @@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 {
> status = "disabled";
> };
>
> + pcie3x4: pcie@fe150000 {
> + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x00 0x0f>;
> + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
> + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
> + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk",
> + "aux", "pipe";
> + device_type = "pci";
> + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
> + <0 0 0 2 &pcie3x4_intc 1>,
> + <0 0 0 3 &pcie3x4_intc 2>,
> + <0 0 0 4 &pcie3x4_intc 3>;
> + linux,pci-domain = <0>;
> + max-link-speed = <3>;
> + msi-map = <0x0000 &its1 0x0000 0x1000>;
> + num-lanes = <4>;
> + phys = <&pcie30phy>;
> + phy-names = "pcie-phy";
> + power-domains = <&power RK3588_PD_PCIE>;
> + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
> + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
> + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
> + reg = <0xa 0x40000000 0x0 0x00400000>,
> + <0x0 0xfe150000 0x0 0x00010000>,
> + <0x0 0xf0000000 0x0 0x00100000>;
> + reg-names = "dbi", "apb", "config";
> + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
> + reset-names = "pwr", "pipe";
> + status = "disabled";
> +
> + pcie3x4_intc: legacy-interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
> + };
> + };
> +
> + pcie3x2: pcie@fe160000 {
> + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x10 0x1f>;
> + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
> + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
> + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk",
> + "aux", "pipe";
> + device_type = "pci";
> + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> + interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
> + <0 0 0 2 &pcie3x2_intc 1>,
> + <0 0 0 3 &pcie3x2_intc 2>,
> + <0 0 0 4 &pcie3x2_intc 3>;
> + linux,pci-domain = <1>;
> + max-link-speed = <3>;
> + msi-map = <0x1000 &its1 0x1000 0x1000>;
> + num-lanes = <2>;
> + phys = <&pcie30phy>;
> + phy-names = "pcie-phy";
> + power-domains = <&power RK3588_PD_PCIE>;
> + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
> + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
> + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
> + reg = <0xa 0x40400000 0x0 0x00400000>,
> + <0x0 0xfe160000 0x0 0x00010000>,
> + <0x0 0xf1000000 0x0 0x00100000>;
> + reg-names = "dbi", "apb", "config";
> + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
> + reset-names = "pwr", "pipe";
> + status = "disabled";
> +
> + pcie3x2_intc: legacy-interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
> + };
> + };
> +
> pcie2x1l0: pcie@fe170000 {
> compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> #address-cells = <3>;
> @@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 {
> rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
> status = "disabled";
> };
> +
> + pcie30phy: phy@fee80000 {
> + compatible = "rockchip,rk3588-pcie3-phy";
> + reg = <0x0 0xfee80000 0x0 0x20000>;
> + #phy-cells = <0>;
> + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
> + clock-names = "pclk";
> + resets = <&cru SRST_PCIE30_PHY>;
> + reset-names = "phy";
> + rockchip,pipe-grf = <&php_grf>;
> + rockchip,phy-grf = <&pcie30_phy_grf>;
> + status = "disabled";
> + };
> };
> --
> 2.40.1
>
>
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