Re: [PATCH 15/15] arm64: dts: qcom: sm6115: Add VDD_CX to GPU_CCC

[Dmitry Baryshkov]

On Tue, 18 Jul 2023 at 15:48, Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> wrote:
>
> On 18.07.2023 13:56, Stephan Gerhold wrote:
> > On Mon, Jul 17, 2023 at 09:18:21PM +0200, Konrad Dybcio wrote:
> >> On 17.07.2023 19:23, Stephan Gerhold wrote:
> >>> On Mon, Jul 17, 2023 at 07:11:33PM +0200, Konrad Dybcio wrote:
> >>>> On 17.07.2023 18:56, Stephan Gerhold wrote:
> >>>>> On Mon, Jul 17, 2023 at 06:50:18PM +0200, Konrad Dybcio wrote:
> >>>>>> On 17.07.2023 18:28, Stephan Gerhold wrote:
> >>>>>>> On Mon, Jul 17, 2023 at 05:19:22PM +0200, Konrad Dybcio wrote:
> >>>>>>>> The GPU_CC block is powered by VDD_CX. Describe that.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
> >>>>>>>> ---
> >>>>>>>>  arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 ++
> >>>>>>>>  1 file changed, 2 insertions(+)
> >>>>>>>>
> >>>>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> >>>>>>>> index 29b5b388cd94..bfaaa1801a4d 100644
> >>>>>>>> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> >>>>>>>> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> >>>>>>>> @@ -1430,6 +1430,8 @@ gpucc: clock-controller@5990000 {
> >>>>>>>>                        clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> >>>>>>>>                                 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
> >>>>>>>>                                 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
> >>>>>>>> +                      power-domains = <&rpmpd SM6115_VDDCX>;
> >>>>>>>> +                      required-opps = <&rpmpd_opp_low_svs>;
> >>>>>>>
> >>>>>>> Where is this required-opp coming from? The clocks in gpucc seem to have
> >>>>>>> different voltage requirements depending on the rates, but we usually
> >>>>>>> handle that in the OPP tables of the consumer.
> >>>>>> The only lower levels defined for this SoC are VDD_MIN and VDD_RET,
> >>>>>> but quite obviously the GPU won't work then
> >>>>>>
> >>>>>
> >>>>> The levels needed for the GPU clocks to run should be in the GPU OPP
> >>>>> table though, just like e.g. sdhc2_opp_table for the SDCC clocks.
> >>>>>
> >>>>> I still don't really understand why this is specified here. :)
> >>>> The GPU_CC block needs this rail to be at a certain power level for
> >>>> register access. This describes that requirement.
> >>>>
> >>>
> >>> Can you show where this is defined downstream? On a quick look I didn't
> >>> see something like that anywhere. Or is this from some secret
> >>> documentation?
> >> As far as downstream goes, you can notice that no branch's or RCG's
> >> vdd tables ever define a level lower than the one I mentioned.
> >>
> >
> > As far as I can tell the vdd tables are only used when the clock is
> > actually enabled though, not for writing to registers while they are
> > disabled.
> Maybe, but you can also notice that even XO rates require at least
> SVS_LOW to function.

But the vdd tables are related to clock rates, which, in the upstream
design, should be voted by the consumers, not by the clock driver.


-- 
With best wishes
Dmitry