[PATCH] drm/radeon: ERROR: that open brace { should be on the previous line

[shijie001]

Fix eight occurrences of the checkpatch.pl error:
ERROR: that open brace { should be on the previous line
ERROR: space prohibited before that close parenthesis ')'
ERROR: spaces required around that '?' (ctx:VxW)

Signed-off-by: Jie Shi <shijie001@xxxxxxxxxx>
---
 drivers/gpu/drm/radeon/sumo_dpm.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c 
b/drivers/gpu/drm/radeon/sumo_dpm.c
index f74f381af05f..8af793c89fd1 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -33,8 +33,7 @@
 #define SUMO_MINIMUM_ENGINE_CLOCK 800
 #define BOOST_DPM_LEVEL 7

-static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
-{
+static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = {
     SUMO_UTC_DFLT_00,
     SUMO_UTC_DFLT_01,
     SUMO_UTC_DFLT_02,
@@ -52,8 +51,7 @@ static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
     SUMO_UTC_DFLT_14,
 };

-static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
-{
+static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = {
     SUMO_DTC_DFLT_00,
     SUMO_DTC_DFLT_01,
     SUMO_DTC_DFLT_02,
@@ -109,11 +107,11 @@ static void sumo_mg_clockgating_enable(struct 
radeon_device *rdev, bool enable)
     local1 = RREG32(CG_CGTT_LOCAL_1);

     if (enable) {
-        WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & 
~CGCG_CGTT_LOCAL0_MASK) );
-        WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & 
~CGCG_CGTT_LOCAL1_MASK) );
+        WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & 
~CGCG_CGTT_LOCAL0_MASK));
+        WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & 
~CGCG_CGTT_LOCAL1_MASK));
     } else {
-        WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | 
(local0 & ~CGCG_CGTT_LOCAL0_MASK) );
-        WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | 
(local1 & ~CGCG_CGTT_LOCAL1_MASK) );
+        WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | 
(local0 & ~CGCG_CGTT_LOCAL0_MASK));
+        WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | 
(local1 & ~CGCG_CGTT_LOCAL1_MASK));
     }
 }

@@ -702,9 +700,9 @@ static void sumo_post_notify_alt_vddnb_change(struct 
radeon_device *rdev,
     u32 nbps1_new = 0;

     if (old_ps != NULL)
-        nbps1_old = (old_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
+        nbps1_old = (old_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;

-    nbps1_new = (new_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
+    nbps1_new = (new_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;

     if (nbps1_old == 0 && nbps1_new == 1)
         sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);