PCI: cadence: Allow async probe

[Li Chen]

From: Li Chen <lchen@xxxxxxxxxxxxx>

I observed that on Ambarella SoC, which also utilizes
the Cadence controller, the boot time increases by 1
second when no endpoints (including switch) are connected
to PCIe. This increase is caused by cdns_pcie_host_wait_for_link.

Enabling async probe can eliminate this boot time increase.

I guess other platforms also has this issue.

Signed-off-by: Li Chen <lchen@xxxxxxxxxxxxx>
---
 drivers/pci/controller/cadence/pcie-cadence-plat.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
index e091fef9c919..5177f18e1dfc 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
@@ -174,6 +174,7 @@ static struct platform_driver cdns_plat_pcie_driver = {
 		.name = "cdns-pcie",
 		.of_match_table = cdns_plat_pcie_of_match,
 		.pm	= &cdns_pcie_pm_ops,
+		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
 	},
 	.probe = cdns_plat_pcie_probe,
 	.shutdown = cdns_plat_pcie_shutdown,
-- 
2.34.1