Re: [PATCH v4] riscv: Discard vector state on syscalls

[Andy Chiu]

On Thu, Jun 29, 2023 at 10:22 PM Björn Töpel <bjorn@xxxxxxxxxx> wrote:
>
> From: Björn Töpel <bjorn@xxxxxxxxxxxx>
>
> The RISC-V vector specification states:
>   Executing a system call causes all caller-saved vector registers
>   (v0-v31, vl, vtype) and vstart to become unspecified.
>
> The vector registers are set to all 1s, vill is set (invalid), and the
> vector status is set to Dirty.
>
> That way we can prevent userspace from accidentally relying on the
> stated save.
>
> Rémi pointed out [1] that writing to the registers might be
> superfluous, and setting vill is sufficient.
>
> Link: https://lore.kernel.org/linux-riscv/12784326.9UPPK3MAeB@xxxxxxxxxxxxxxxxx/ # [1]
> Suggested-by: Darius Rad <darius@xxxxxxxxxxxx>
> Suggested-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
> Suggested-by: Rémi Denis-Courmont <remi@xxxxxxxxxx>
> Signed-off-by: Björn Töpel <bjorn@xxxxxxxxxxxx>

Thanks,
Reviewed-by: Andy Chiu <andy.chiu@xxxxxxxxxx>