RE: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro

[Biju Das]

Hi Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@xxxxxxxxx>
> Sent: Tuesday, July 4, 2023 9:36 AM
> To: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Cc: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>; Magnus Damm
> <magnus.damm@xxxxxxxxx>; Rob Herring <robh+dt@xxxxxxxxxx>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx>; Linus Walleij
> <linus.walleij@xxxxxxxxxx>; linux-renesas-soc@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-riscv@xxxxxxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; linux-gpio@xxxxxxxxxxxxxxx; Prabhakar Mahadev
> Lad <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> Subject: Re: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> RZG2L_GPIO_PORT_PACK() macro
> 
> Hi Biju,
> 
> On Tue, Jul 4, 2023 at 9:30 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> wrote:
> >
> > Hi Prabhakar,
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@xxxxxxxxx>
> > > Sent: Friday, June 30, 2023 1:05 PM
> > > To: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>; Magnus Damm
> > > <magnus.damm@xxxxxxxxx>
> > > Cc: Rob Herring <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski
> > > <krzysztof.kozlowski+dt@xxxxxxxxxx>; Linus Walleij
> > > <linus.walleij@xxxxxxxxxx>; linux-renesas-soc@xxxxxxxxxxxxxxx;
> > > devicetree@xxxxxxxxxxxxxxx; linux-riscv@xxxxxxxxxxxxxxxxxxx; linux-
> > > kernel@xxxxxxxxxxxxxxx; linux-gpio@xxxxxxxxxxxxxxx; Biju Das
> > > <biju.das.jz@xxxxxxxxxxxxxx>; Prabhakar
> > > <prabhakar.csengg@xxxxxxxxx>; Prabhakar Mahadev Lad
> > > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > Subject: [RFC PATCH 1/4] pinctrl: renesas: rzg2l: Include pinmap in
> > > RZG2L_GPIO_PORT_PACK() macro
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Currently we assume all the port pins are sequential ie always PX_0
> > > to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins
> > > P19_1 to
> > > P28_5 which have holes in them, for example only one pin on port19
> > > is available and that is P19_1 and not P19_0.
> > >
> > > So to handle such cases include pinmap for each port which would
> > > indicate the pin availability on each port. With this we also get
> > > additional pin validation, for example on the RZ/G2L SOC P0 has two
> > > pins
> > > P0_1 and P0_0 but with DT/SYSFS could use the P0_2-P0_7.
> > >
> > > While at it, update rzg2l_validate_gpio_pin() to use the port pinmap
> > > to validate the gpio pin.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > > ---
> > >  drivers/pinctrl/renesas/pinctrl-rzg2l.c | 167
> > > ++++++++++++------------
> > >  1 file changed, 86 insertions(+), 81 deletions(-)
> > >
> > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > index 9511d920565e..a0c2e585e765 100644
> > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > @@ -67,10 +67,12 @@
> > >                                        PIN_CFG_FILCLKSEL)
> > >
> > >  /*
> > > - * n indicates number of pins in the port, a is the register index
> > > - * and f is pin configuration capabilities supported.
> > > + * m indicates the bitmap of supported pins, n indicates number
> > > + * of pins in the port, a is the register index and f is pin
> > > + * configuration capabilities supported.
> > >   */
> > > -#define RZG2L_GPIO_PORT_PACK(

, a, f)        (((n) << 28) | ((a) <<
> 20) |
> > > (f))
> > > +#define RZG2L_GPIO_PORT_PACK(m, n, a, f)     ((UL(m) << 32) |
> (UL(n) << 28)
> > > | ((a) << 20) | (f))
> > > +#define RZG2L_GPIO_PORT_GET_PINMAP(x)        (((x) & GENMASK(39,
> 32)) >> 32)
> > >  #define RZG2L_GPIO_PORT_GET_PINCNT(x)        (((x) & GENMASK(30,
> 28)) >> 28)
> > >  #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >>
> > > 20)  #define RZG2L_GPIO_PORT_GET_CFGS(x)  ((x) & GENMASK(19, 0)) @@
> > > -129,7 +131,7 @@ struct rzg2l_dedicated_configs {
> > >
> > >  struct rzg2l_pinctrl_data {
> > >       const char * const *port_pins;
> > > -     const u32 *port_pin_configs;
> > > +     const u64 *port_pin_configs;
> >
> > Can this be SoC specific? Only for RZ/Five you need this changes.
> > Others SoCs like RZ/{G2L,G2LC,V2L and G2UL) still work with u32* as
> > there is no holes. With this change memory usage is doubled as we
> > change from
> > u32->u64.
> >
> This is to avoid writing to undocumented registers so I have added for
> all the SoCs. For example on the RZ/G2L SOC P0 has two pins P0_1 and
> P0_0 but DT/SYSFS could use the P0_2-P0_7. This patch restricts users to
> use only available GPIO pins.

I guess that still can be achieved, as the below macro has valid
pins info??

#define RZG2L_GPIO_PORT_GET_PINCNT(x)	(((x) & GENMASK(30, 28)) >> 28)

if (!(BIT(bit) & GENMASK(RZG2L_GPIO_PORT_GET_PINCNT(x), 0))
return -EINVAL;

Cheers,
Biju