Re: [PATCH v8 00/14] cxl/pci: Add support for RCH RAS error handling

[Dan Williams]

Terry Bowman wrote:
> This patchset enables CXL RCH error handling. This is necessary because RCH
> downstream port protocol error handling is implemented uniquely and not
> currently supported. These patches address the following:
> 
>    * Discovery and mapping of RCH downstream port AER registers.
> 
>    * AER portdrv changes to support CXL RCH protocol errors. 
> 
>    * Interrupt setup specific to RCH mode: enabling RCEC internal
>      errors and disabling root port interrupts.
> 
> Changes in V8:
>   - Rebased onto: commit
>     0c0df63177e3 ("Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxl")
>   - cxl/port: Pre-initialize component register mappings
>     - Added patch to pre-initialize component register mappings.
>   - cxl/pci: Remove Component Register base address from
>     - Separated removal of Component Register base address in struct
>     cxl_dev_state to not break functionality.
>   - cxl/hdm: Use stored Component Register mappings to map HDM decoder
>     capability
>     - Implemented a less strict check in devm_cxl_setup_hdm(), be tolerant
>     if HDM decoder registers are not implemented.
>   - cxl/pci: Map RCH downstream AER registers for  logging protocol errors
>     - Fixed uninitialized access of map->dev in cxl_dport_map_regs().
>   - PCI/AER: Forward RCH downstream port-detected errors to the CXL.mem
>     dev handler
>     - Fix typo in patch description.
>   - cxl/pci: Update CXL error logging to use RAS register address
>     - Fix typo in patch description.

Hey Terry, thank you for turning this around so quickly. I will have a
look and see if this is suitable as a follow-up merge for v6.5 next week
since it would be nice to finish this off this cycle, but no promises.