[tip: timers/core] dt-bindings: timers: Add Ralink SoCs timer

From: tip-bot2 for Sergio Paracuellos
Date: Mon Jun 26 2023 - 05:13:49 EST


The following commit has been merged into the timers/core branch of tip:

Commit-ID: 6d0d4df8e7e1fe22d961d667c2bfa40c3d5022e8
Gitweb: https://git.kernel.org/tip/6d0d4df8e7e1fe22d961d667c2bfa40c3d5022e8
Author: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
AuthorDate: Tue, 20 Jun 2023 12:02:31 +02:00
Committer: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
CommitterDate: Fri, 23 Jun 2023 09:33:43 +02:00

dt-bindings: timers: Add Ralink SoCs timer

Add YAML documentation for the timer which is present on Ralink SoCs.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20230620100231.1412582-1-sergio.paracuellos@xxxxxxxxx
---
Documentation/devicetree/bindings/timer/ralink,rt2880-timer.yaml | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/ralink,rt2880-timer.yaml

diff --git a/Documentation/devicetree/bindings/timer/ralink,rt2880-timer.yaml b/Documentation/devicetree/bindings/timer/ralink,rt2880-timer.yaml
new file mode 100644
index 0000000..daa7832
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ralink,rt2880-timer.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/ralink,rt2880-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Timer present in Ralink family SoCs
+
+maintainers:
+ - Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
+
+properties:
+ compatible:
+ const: ralink,rt2880-timer
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@100 {
+ compatible = "ralink,rt2880-timer";
+ reg = <0x100 0x20>;
+
+ clocks = <&sysc 3>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <1>;
+ };
+...